| Name | Content |
| MEM4MB (M4) | Specify memory size |
| DAC18B (DB) | Use 18-bit D / A converter for digital output |
| VER | Version number |
| MVOL | Master volume |
| RBL | Ring buffer length |
| RBP | Ring buffer start address |
| MOFULL (OF) | Full output FIFO |
| MOEMP (OE) | Output FIFO empty |
| MIOVF (IO) | Input FIFO overflow |
| MIFULL (IF) | Input FIFO full |
| MIEMP (IE) | Input FIFO empty |
| MIBUF | MIDI input data buffer |
| MOBUF | MIDI output data buffer |
| MSLC | Monitor slot |
| CA | Call address |
| DMEA | DMA transfer start memory address |
| DRGA | DMA transfer start register address |
| DGATE (GA) | DMA transfer gate 0 clear |
| DDIR (DI) | DMA transfer direction |
| DEXE (EX) | Start DMA transfer |
| DTLG | DMA transfer data count |
| TACTL | Timer A prescaler control |
| TIMA | Timer A count data |
| TBCTL | Timer B prescaler control |
| TIMB | Timer B count data |
| TCCTL | Timer C prescaler control |
| TIMC | Timer C count data |
| SCIEB | Enable sound CPU interrupt |
| SCIPD | Sound CPU interrupt request |
| SCIRE | Sound CPU interrupt reset |
| SCILV0 | Sound CPU interrupt level bit0 |
| SCILV1 | Sound CPU interrupt level bit1 |
| SCILV2 | Sound CPU interrupt level bit2 |
| MCIEB | Main CPU interrupt enabled |
| MCIPD | Main CPU interrupt request |
| MCIRE | Main CPU interrupt reset |