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Table 4.31 EFSDL and EFPAN register addresses corresponding to each EFREG and EXTS
Source Address Data source address data
7654321076543210
EFREG0100017HEFSDL0EFPAN0EFREG9100137HEFSDL9EFPAN9
EFREG1100037HEFSDL1EFPAN1EFREG10100157HEFSDL10EFPAN10
EFREG2100057HEFSDL2EFPAN2EFREG11100177HEFSDL11EFPAN11
EFREG3100077HEFSDL3EFPAN3EFREG12100197HEFSDL12EFPAN12
EFREG4100097HEFSDL4EFPAN4EFREG131001B7HEFSDL13EFPAN13
EFREG51000B7HEFSDL5EFPAN5EFREG141001D7HEFSDL14EFPAN14
EFREG61000D7HEFSDL6EFPAN6EFREG151001F7HEFSDL15EFPAN15
EFREG71000F7HEFSDL7EFPAN7EXTS0100217HEFSDL16EFPAN16
EFREG8100117HEFSDL8EFPAN8EXTS1100237HEFSDL17EFPAN17

MVOL [3: 0] (W); Master VOLume
Indicates the output master volume to the D / A converter.
This is to control the overall output level. Clipping noise does not disappear even if the gain is lowered by lowering the "MVOL" setting value for the output overflow (To eliminate clipping noise) Please reset "DISDL" and "EFSDL" to eliminate the overflow).

DAC18B (W); DAC out 18Bit
Set this bit to “1B” when the digital output is used as an interface of an 18-bit D / A converter. For 16 bits, set "0B". (Basically, a 16-bit type D / A converter is connected, so set "0B" in the register.)

Figure 4.57: Connection between SCSP and DAC


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