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- Registers are explained below.
∙ There are two types of interrupts: a part that manages interrupts for the main (register named MC ~) and a part that manages interrupts for the sound CPU (register named SC ~).
- SCIPD[10:0] ; Sound-Cpu Interrupt PenDing
- This register (interrupt flag) monitors interrupts to the sound CPU. When an interrupt request occurs, the corresponding interrupt request flag is set to "1B", so the CPU can know which interrupt is occurring by reading the "SCIPD" register. In addition, interrupt requests are monitored sequentially regardless of the interrupt enable register ("SCIEB ") setting. The corresponding flag can be reset by the interrupt reset register ("SCIRE"). Only bit 5 can be read and written, all others are read-only. Setting bit 1 to “1B” interrupts the sound CPU. However, writing "0B" is invalid.
- SCIEB [10: 0] (R / W); Sound-Cpu Interrupt EnaBle
- Interrupt enable register for sound CPU. Enable hardware interrupt for the corresponding bit with the "1B" set. Whether or not an interrupt has occurred can be determined by reading "SCIPD" regardless of the "SCIEB" setting. Setting "0B" is unauthorized.
- SCIRE [10: 0] (W); Sound-Cpu Interrupt REset
- Interrupt request reset flag to the sound CPU. Resets the hardware interrupt request for the corresponding bit with the "1B" set. (By setting "1B" to "SCIRE" corresponding to the bit for which an interrupt has occurred, "SCIPD" Will also change from "1B" to "0B").
- MCIPD [10: 0] (R); Main Cpu Interrupy PenDing
- This is a register (interrupt flag) that monitors interrupts to the main CPU. When an interrupt request occurs, the corresponding interrupt request flag changes to "1B", so the CPU can know which interrupt is occurring by reading the "MCIPD" register. Also, interrupt requests are monitored sequentially regardless of the interrupt enable register ("MCIEB") setting. The corresponding flag can be reset by the interrupt reset register ("MCIRE"). Only bit 5 can be read and written, all others are read-only. When bit 5 is set to "1B", the main CPU is interrupted. However, writing "0B" is invalid.
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