SEGA SATURN DEVELOPER'S MANUAL

MCIEB [10: 0] (R); Main Cpu Interrupy EnaBle: Interrupt enable register for main CPU. Enable hardware interrupt for the corresponding bit with the "1B" set. Whether or not an interrupt has occurred can be determined by reading "MCIPD" regardless of the "MCIEB" setting. Setting "0B" is unauthorized.
MCIRE [10: 0] (R); Main Cpu Interrupt REset: Interrupt request reset flag to the main CPU. The hardware interrupt request for the corresponding bit is reset when the bit is set to “1” (for the bit where the interrupt is generated, “MCIPD” is set by setting “1B” to “MCIRE” corresponding to the bit. Will also change from "1B" to "0B").
Figure 4.63 Interrupt register bit support