Condition: Timer A interrupts the main CPU, and the sound CPU
When applying level 6 interrupt 

Procedure: Set all interrupts as if they are not currently interrupted.
After completion, set the timer. 

1: Set the sound CPU interrupt level to 6.
Level 6 is “110B” as a 3-bit code.
Also, since the bit for managing the timer A interrupt is bit 6,
"0B" in bit 6 of "SCILV0"
* ("00H" in bytes at address 100425H, or "0000H" in words at address 100424H)
"1B" in bit 6 of "SCILV0"
(The byte at address 100427H is "40H", or the word at address 100426H is "0040H")
"1B" in bit 6 of "SCILV0"
(10040H at byte "40H", or 100428H at word "0040H")
Set. This completes the interrupt level setting. 

2: “MCIEB” and “SCIEB” records so that the main and sound CPUs are interrupted.
パ ラ メ ー タ Set parameters for the register.
"MCIEB" register so that timer A interrupts the main CPU
Write "1B" to bit 6 of.
⿟ ("40H" in bytes at address 10042BH, or "0040H" in words at address 10042AH)
Also, bit 6 of “SCIEB” is set so that the sound CPU is similarly interrupted.
Write “1B”.
⿟ ("40H" in bytes at address 100421FH, or "0040H" in words at address 100041EH)
Furthermore, by setting a parameter in the timer, the count is started immediately after that.
First, an interrupt will occur if an overflow occurs. 

3: To cancel the interrupt, use the main and sound CPU reset registers.
Please use.