SEGA SATURN DEVELOPER'S MANUAL

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DMA transfer register

DMA with built-in SCSP can only transfer between SCSP built-in control register and sound memory. For this reason, the maximum number of continuous transfer bytes is 3812 bytes (EE4H) (100,000H to 100EE3H memory space is allocated to the internal registers). The DMA-related registers described below are prohibited from being changed by DMA transfer. During DMA transfer, the address always changes in the increasing direction.
The precautions for executing DMA transfer are shown below.
While

DMA is running, the operating speed of the main CPU and sound CPU may drop.
Access by DMA transfer to the DMA controller control register is absolutely prohibited. If this transfer is performed, the operation cannot be guaranteed at all.
DMA transfer is word (16bit) transfer.

DGATE (R / W); Dma GATE (and "0")

A block diagram of the DMA controller is shown in Figure 4.66. Initializes any area in the SCSP built-in control register or sound memory to "0". When this bit is "1B", "0" clear is executed ("DEXE" must be executed to actually start).
∙ Transfer data deletion ("0" write) by DGATE does not affect the data at the transfer source. There is no loss of data.

Figure 4.66 DMA controller block diagram

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