PDR2 is a 7-bit register that stores the data of peripheral port 2 (P2). Whether each bit of PDR2 is an input port or an output port depends on the DDR2 setting. By writing data to this register, the pin status of the port set as output can be changed. By reading this register, the pin status of the port set as input can be read. For ports set to output, the value written to PDR2 is read, not the pin status. Byte access from SH-2.
IOSEL1 (W): I / O SELect 1
Set peripheral port 1 (P1) to SMPC control mode or SH-2 direct mode. When "0" is written, SMPC control mode is set. When "1" is written, SH-2 direct mode is set. Byte access from SH-2.
IOSEL2 (W): I / O SELect 2
Set peripheral port 2 (P2) to SMPC control mode or SH-2 direct mode. When "0" is written, SMPC control mode is set. When "1" is written, SH-2 direct mode is set. Byte access from SH-2.
Table 1.4 IOSEL function
bit
function
0
Set to SMPC control mode (initial value)
1
Set to SH-2 direct mode
Refer to Chapter 3 for details of each mode.
EXLE1 (W): EXternal Latch Enable 1
This bit is used to set whether bit 6 of peripheral port 1 (P1) is used as an input for PAD interrupt or VDP2 external latch Writing "0" disables it, and bit 6 of peripheral port 1 is set as a normal I / O port. Writing "1" enables it, and bit 6 of peripheral port 1 can be used as a PAD interrupt input or VDP2 external latch input. Byte access from SH-2.