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SCU DSP Alambra Instruction Manual

'94/07/08

Contents

1. Assembler functions
2. Run the assembler
3. Program description format
4. Instruction list
5. Sample program

1. Outline of assembler functions

This assembler is for generating instruction codes for DSP, and is intended to run on MS-DOS and UNIX. The output code is Motorola's S format and the code is output directly, so no link is required.
The DSP assembler requires a lot of hardware knowledge, so please familiarize yourself with the DSP hardware before using the assembler.

2. Run the assembler

dspasm [option] <source file name>
    The following can be specified for the
  1. option. (File creation is only successful)
    -l [file name]: List output specification
    -a [file name]: Data format output specification for SH assembler
    -c [file name]: C data format output specification
    -m: Specify when using the MODEL M development environment
  2. The source file name has no default extension. The
  3. error is displayed only for the first detected one. Repeat correction and assembly until no error occurs.

3. Program description format

[Label] [△ Operation [△ Operand]] ... [Comment]
Example: LABEL: MOV MC0, X; comment

(1) Label

(2) Operation

(3) Operand

(4) Comments

* Notes on writing * About reserved words * About numerical calculation

Operational relation

+ … addition
- … Subtraction
* … Multiplication
/ … division
% … Exclusion
‾ … Bit negation
& … Bit product
| … bit sum
^ … Exclusive bit sum
<<… Shift left
>>… Shift right

Priority

1. + - ~ (unary operator)
2. * / %
3. + -
4. <<>>
5. &
6. | ^

4. Instruction list

  1. Operation instruction
    NOP AND OR XOR ADD SUB AD2 SR RR SL RL RL8 CLR MOV
  2. Load immediate instruction
    MVI
  3. DMA instruction
    DMA DMAH
  4. JUMP instruction
    JMP
  5. LOOP BOTTOM instruction
    BTM LPS
  6. END instruction
    END ENDI

Pseudo-instruction

5. Sample program

(1) When copying the contents of DSP internal RAM0 to internal RAM1.

; ------- sample (1) start -------

COPY_SIZE = 12; Copy size
RAM0_ADR = $ 00; Copy source address
RAM1_ADR = $ 00; Copy destination address

MOV RAM0_ADR, CT0; Set the RAM0 copy source address
MOV RAM1_ADR, CT1; Set the copy destination address of RAM1
MOV COPY_SIZE-1, LOP; Set transfer size -1 in LOP register
LPS; 1 instruction loop execution
MOV MC0, MC1; Transfer from RAM0 to RAM1
ENDI

; ------- sample (1) end -------

(2) When calculating 2 × 3 + 4 × 5. (RAM0 x RAM1 + RAM0 x RAM1 = RAM2) (sample 2b is an optimized version of 2a)

; ------- sample (2a) start -------

RAM0_ADR = $ 00; 2, 4 First storage address
RAM1_ADR = $ 00; 3, 5 Storage address head
RAM2_ADR = $ 00; Result storage address

MOV RAM0_ADR, CT0; Set RAM0 address
MOV RAM1_ADR, CT1; Set the address of RAM1
MVI # 2, MC0; Set “2” to RAM0
MVI # 3, MC1; Set “3” to RAM1
MVI # 4, MC0; Set “4” to RAM0
MVI # 5, MC1; Set “5” to RAM1
MOV RAM0_ADR, CT0; Set RAM0 address
MOV RAM1_ADR, CT1; Set the address of RAM1
MOV RAM2_ADR, CT2; Set the address of RAM2
MOV MC0, X; Data transfer from RAM0 to RX
MOV MC1, Y; Data transfer from RAM1 to RY
MOV MUL, P; Stores RX and RY integration results in PH and PL
MOV MC0, X; Data transfer from RAM0 to RX
MOV MC1, Y; Data transfer from RAM1 to RY
CLR A; Set “0” to ACH and ACL
AD2 MOV ALU, A; Addition result of PH, PL and ACH, ACL is stored in ACH, ACL
MOV MUL, P; Stores RX and RY integration results in PH and PL
AD2 MOV ALL, MC2; Addition result of PH, PL and ACH, ACL is stored in RAM2.
ENDI

; ------- sample (2a) end -------
; ------- sample (2b) start -------

RAM0_ADR = $ 00; 2, 4 First storage address
RAM1_ADR = $ 00; 3, 5 Storage address head
RAM2_ADR = $ 00; Result storage address

MOV RAM0_ADR, CT0
MOV RAM1_ADR, CT1
MVI # 2, MC0
MVI # 3, MC1
MVI # 4, MC0
MVI # 5, MC1
MOV RAM0_ADR, CT0
MOV RAM1_ADR, CT1
MOV MC0, X MOV MC1, Y MOV RAM2_ADR, CT2
MOV MC0, X MOV MUL, P MOV MC1, Y CLR A
AD2 MOV MUL, P MOV ALU, A
AD2 MOV ALL, MC2
ENDI

; ------- sample (2b) end -------

(3) When calculating movement processing for a matrix. (RAM0 × RAM1 = RAM2)

 / M00 M01 M02 M03 \ / 100x \ / M00 M01M02 M03 \
| M10 M11 M12 M13 || 010y | → | M10 M11 M12 M13 |
 \ M20 M21 M22 M23 / | 001z | \ M20 M21M22 M23 /
 , \ 0001 /

; ------- sample (3) start -------

DATA_TOP = $ 10000 >> 2; The address of the external memory is in 4-byte units
MAT_SIZE = $ 0C; array size
RAM0_ADR = $ 00; Start address for storing the movement amount of X, Y, Z
RAM1_ADR = $ 00; Work address for array
RAM2_ADR = $ 00; Original array address

; (Transfer array with movement amount set from external memory to RAM0)
;
MVI DATA_TOP, RA0
MOV RAM0_ADR, CT0
DMA D0, MC0, # $ 02
;
; (Copy of array to operate from RAM2 to RAM1)
MOV RAM2_ADR, CT2
MOV RAM1_ADR, CT1
MOV MAT_SIZE-1, LOP
LPS
MOV MC2, MC1
WAITING:
JMP T0, WAITING
;
; (Array calculation execution)
MOV RAM0_ADR, CT0
MOV RAM1_ADR, CT1
MOV MC0, X MOV MC1, Y
MOV MC0, X MOV MUL, P MOV MC1, Y CLR A
AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM0_ADR, CT0
AD2 MOV MUL, P MOV MC1, Y MOV ALU, A MOV # 1, RX
AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM2_ADR + 3, CT2
AD2 MOV MC0, X MOV MUL, P MOV MC1, Y CLR A MOV ALL, MC2
AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM0_ADR, CT0
AD2 MOV MUL, P MOV MC1, Y MOV ALU, A MOV # 1, RX
AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM2_ADR + 7, CT2
AD2 MOV MC0, X MOV MUL, P MOV MC1, Y CLR A MOV ALL, MC2
AD2 MOV MC0, X MOV MUL, P MOV MC1, Y MOV ALU, A MOV RAM0_ADR, CT0
AD2 MOV MUL, P MOV MC1, Y MOV ALU, A MOV # 1, RX
AD2 MOV MUL, P MOV ALU, A MOV RAM2_ADR + 11, CT2
AD2 MOV ALL, MC2
ENDI

; ------- sample (3) end -------
that's all
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