Figure 1.17 shows the interrupt mask register map. When this bit is 0, interrupts are not masked and interrupts are generated on demand. When 1, the interrupt is masked, so no interrupt is generated. The details from bit0 (number 15 in the figure) to bit13 (number 2 in the figure) are explained in detail in Chapter 3.
Figure 1.17 Interrupt mask register map
■ Interrupt status register
Figure 1.18 shows the interrupt status register map. This register is a readable / writable register. When reading, if bit data is 0, it indicates that no interrupt has occurred, and if it is 1, it indicates that an interrupt has occurred. When writing, writing 0 resets the interrupt and writing 1 holds the current interrupt status. The details of this register are described in detail in Chapter 3.
