Return to previous page ｜ Return to menu ｜ Go to next page

A-Bus interrupt acknowledge register

Figure 1.19 shows a map of A-Bus interrupt acknowledge. This bit is readable and writable, and has different meanings when reading and writing. Details are given in Chapter 3.

Figure 1.19 A-Bus interrupt acknowledge register map

A-Bus setting register

Figure 1.20 shows the map of A-Bus setting register. Each prefetch valid bit, precharge insertion bit, and external wait valid bit are invalid when 0 and valid when 1. Details are given in Chapter 3.

Figure 1.20 A-Bus setting register map

Return to previous page ｜ Return to menu ｜ Go to next page