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Figure 3.12 High and low level DMA operation

Also, when the interrupting and operating bit is 0, it is recognized that the DMA operation is stopped.
Figure 3.13 shows details of the access, interrupt, standby, and operation registers.

Figure 3.13 DMA status register (register: DSTA) Initial value 00000000H

DMA DSP bus access flag (1 [bit 22] in Figure 3.13)
DACSD (R) DMA ACceSs DSP-Bus
Indicates whether the DSP bus is accessed during DMA. 1 indicates access while 0 indicates non-access.

DMA B bus access flag (2 [bit 21] in Figure 3.13)
DACSB (R) DMA ACceSs B-Bus
Indicates whether the B bus is accessed during DMA. 1 indicates access while 0 indicates non-access.

DMA A bus access flag (3 [bit 20] in Figure 3.13)
DACSA (R) DMA ACceSs A-Bus
Indicates whether the A bus is being accessed during DMA. 1 indicates access while 0 indicates non-access.

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