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■ 3.4 Timer register

■ Timer 0 compare register

Figure 3.18 shows the details of the timer 0 compare register. (Timer 0 is a counter that counts up when the H-blank-IN signal is received and is cleared when the V-blank-END signal is received.)

Figure 3.18 Initial value of timer 0 compare register (register: T0C) is undefined

Timer 0 compare data (1 to 10 [bit 9 to 0] in Figure 3.18)
T0C9-0 (W) Timer 0 Compare data bit9-0
Timer 0 interrupt is generated when the value of timer 0 becomes equal to the value of this register.

■ Timer 1 set data register

Figure 3.19 shows the details of the timer 1 set data register. (Timer 1 sets the data in this register upon receipt of the H-blank-IN signal, automatically counts down at 7 MHz, and issues an interrupt when the value of timer 1 reaches 0.)

Figure 3.19 Timer 1 set data register (register: T1S) Initial value undefined

Timer 1 set data (1 to 9 [bit 8 to 0] in Figure 3.19)
T1S8-0 (W) Timer 1 Set data bit8-0
Set the value set to timer 1.

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