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■ Timer 1 mode register

Figure 3.20 shows the details of the timer 1 mode register. This register determines how timer 1 generation is set.

Figure 3.20 Timer 1 mode register (Register: T1MD) Initial value 00000000H

Timer 1 mode bit (1 [bit 8] in Figure 3.20)
T1MD (W) Timer 1 MoDe bit
This bit specifies the occurrence of timer 1. Table 3.6 shows the contents of occurrence.

Table 3.6 Timer 1 occurrence selection 
 T1MD 
 Generation selection contents 
 0 
 Interrupt occurs on every line. 
 1 
 This only occurs on the line specified by timer 0.

Timer enable bit (2 [bit 0] in Figure 3.20)
TENB (W) Timer ENaBle bit
This bit turns the timer operation on / off. Table 3.7 shows the operation details.

Table 3.7 Timer operation contents 
 TENB 
 Timer operation 
 0 
 Timer operation OFF 
 1 
 Timer operation ON

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