SEGA SATURN DEVELOPER'S MANUAL

DSP end interrupt mask bit (10 [bit 5] in Figure 3.21)
IMS5 (W) Interrupt MaSk bit bit5

Specifies whether to mask the DSP end interrupt.

Timer-1 interrupt mask bit (11 [bit 4] in Figure 3.21)
IMS4 (W) Interrupt MaSk bit bit4

Specify whether to mask timer-1 interrupt.

Timer-0 interrupt mask bit (12 [bit 3] in Figure 3.21)
IMS3 (W) Interrupt MaSk bit bit3

Specify whether to mask timer-0 interrupt.

H-blank-IN interrupt mask bit (13 [bit 2] in Figure 3.21)
IMS2 (W) Interrupt MaSk bit bit2

Specifies whether to mask H-blank-IN interrupts.

V-blank-OUT interrupt mask bit (14 [bit 1] in Figure 3.21)
IMS1 (W) Interrupt MaSk bit bit1

Specifies whether to mask V-blank-OUT interrupts.

V-blank-IN interrupt mask bit (15 [bit 0] in Figure 3.21)
IMS0 (W) Interrupt MaSk bit bit0

Specifies whether to mask V-blank-IN interrupts. p>

■ Interrupt status register

Figure 3.22 shows the details of the interrupt status register.

Figure 3.22 Interrupt status register (register: IST) Initial value 00000000H

These status registers are all readable / writable registers, and have the meanings shown in Table 3.8 when reading and writing.