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Table 3.8 Interrupt status bit contents 
 Access 
 Status 
 contents 
 Read 
 0 
 Interrupt Not 
 1 
 Interrupt 
 Write 
 0 
 Reset interrupt 
 1 
 Keep the current interrupt state

External interrupt status bits (1 to 16 [bit31 to 16] in Figure 3.22)
IST31-16 (R / W) Interrupt STatus bit bit31-16
Indicates the status of 16 external interrupts from external interrupt 15 (1 in the figure) to external interrupt 0 (16 in the figure).

Sprite drawing end interrupt status bit (17 [bit 13] in Figure 3.22)
IST13 (R / W) Interrupt STatus bit bit13
Indicates the interrupt status at the end of sprite drawing.

DMA illegal interrupt status bit (18 [bit 12] in Figure 3.22)
IST12 (R / W) Interrupt STatus bit bit12
Indicates the status of DMA illegal interrupt.

Level 0-DMA end interrupt status bit (19 [bit 11] in Figure 3.22)
IST11 (R / W) Interrupt STatus bit bit
Indicates the level 0-DMA end interrupt status.

Level 1-DMA end interrupt status bit (20 [bit 10] in Figure 3.22)
IST10 (R / W) Interrupt STatus bit bit10
Indicates the level 1-DMA end interrupt status.

Level 2-DMA end interrupt status bit (Fig. 3.22, 21 [bit 9])
IST9 (R / W) Interrupt STatus bit bit9
Indicates the status of level 2 DMA end interrupt.

PAD interrupt status bit (22 [bit 8] in Figure 3.22)
IST8 (R / W) Interrupt STatus bit bit8
Indicates the interrupt status from PAD.

System manager interrupt status bit (23 [bit 7] in Figure 3.22)
IST7 (R / W) Interrupt STatus bit bit7
Indicates the status of interrupt from the system manager.

Sound request interrupt status bit (24 [bit 6] in Figure 3.22)
IST6 (R / W) Interrupt STatus bit bit6
Indicates the sound request interrupt status.

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