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3.6 3.6 A-Bus control register

A-Bus interrupt acknowledge register

Figure 3.23 shows the details of the A-Bus interrupt acknowledge register.

Figure 3.23 A-Bus interrupt acknowledge register (register: AIAK) initial value 00000000H

A-Bus interrupt acknowledge (1 [bit 0] in Figure 3.23)
AIACK (R / W) A-Bus Interrupt ACKnowledge
Indicates whether interrupts from devices on A-Bus are enabled / disabled. This bit is a readable / writable bit. Table 3.9 shows the meaning of the bits. When an interrupt is requested, an A-Bus interrupt acknowledge cycle is generated, the interrupt type data (16 bits) is captured, and the current interrupt status can be recognized by its contents. When this cycle occurs, the AIACK bit is set to 0 and the A-Bus interrupt is disabled. To accept an interrupt from A-Bus, the AIACK bit must be reset.

Table 3.9 A-Bus interrupt acknowledge contents 
 Access 
 Status 
 contents 
 Read 
 0 
 A-Bus interrupt Invalid 
 1 
 A-Bus interrupt enabled 
 Export 
 0 
 A-Bus interrupt Invalid 
 1 
 A-Bus interrupt enabled

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