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■ A-Bus setting register

A total of 4 types of space connected to A-Bus, including 3 types of output space of chip select (hereinafter referred to as CS) 0-2 and 1 type of spare space where CS is not output Is available.
∙ Registers related to A-Bus are determined by the connected devices, so they must be set to include all devices. After setting, do not change the value unnecessarily.

CS0,1,2, reserved space A-Bus setting register

Fig. 3.24 shows the details of the A-Bus setting register for CS0 and CS1, and Fig. 3.24 shows the CS-space and spare space.

Figure 3.24 A-Bus setting register [CS0,1 space] (Register: ASR0) Initial value 00000000H

Figure 3.25 A-Bus setting register [CS2, Reserve space] (Register: ASR1) Initial value 00000000H

Read ahead valid bit in CS0 space (1 [bit 31] in Figure 3.24)
A0PRD (W) A-Bus CS0 Previous ReaD bit
This bit determines whether to enable or disable CS0 space data prefetch processing. Data read-ahead processing reduces the time from access start to data output. However, this is valid only for the data stored at the next address of the accessed data, and other addresses are the same as normal access. This bit is 1 for valid and 0 for invalid. Figure 3.26 shows the effect when prefetching is enabled.

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