Figure 3.28 Timing when setting precharge insertion bit after reading
CS0 space external wait valid bit (4 [bit 28] in Figure 3.24) A0EWT (W) A-Bus CS0 External WaiT effective bit
When accessing the CS0 space via A-Bus, a wait can be forced by an external signal, but this bit determines whether to enable or disable the processing. 1 means valid, 0 means invalid. When enabled, the wait continues while the external wait signal is low at the SCU wait sampling point. Figure 3.29 shows the timing chart difference between when external weights are disabled and when they are enabled.
Figure 3.29 Timing differences due to external wait valid bit setting
CS0 space burst cycle wait number setting bits (5 to 8 [bits 27 to 24] in Figure 3.24) A0BW3-0 (W) A-Bus CS0 Burst sycle Wait bit3-0
Set the number of waits for one cycle when performing burst access in CS0 space. Table 3.10 shows the setting values.
