CS0 space bus size setting bit (15 [bit 16] in Figure 3.24) A0SZ (W) A-Bus CS0 bus SiZe bit
Set the A-Bus bus size in the CS0 space. Table 3.13 shows the setting values.
Table 3.13 CS0 space bus size setting values
A0SZ
Bus size setting
0
Specify 16 bit bus
1
Specify 8-bit bus
Read ahead valid bit of CS1 space (16 [bit 15] in Figure 3.24) A1PRD (W) A-Bus CS1 Previous ReaD bit
This bit determines whether to enable or disable CS1 space data read-ahead processing. Data read-ahead processing reduces the time from access start to data output. However, this is valid only for the data stored at the next address of the accessed data, and other addresses remain the same as normal addresses. This bit is 1 for valid and 0 for invalid. See Figure 3.25 for the effect when prefetching is enabled.
Precharge insertion bit after write in CS1 space (17 [bit 14] in Figure 3.24) A1WPC (W) A-Bus CS1 after Write Pre-Charge insert bit
After writing data to
CS1 space, you can insert the unprocessed state for one clock. This bit determines whether the process is enabled or disabled. 1 means valid, 0 means invalid. This bit does not affect the operation after reading. Refer to Figure 3.27 for the operation when this bit is set.
Precharge insertion bit after read in CS1 space (18 [bit 13] in Figure 3.24) A1RPC (W) A-Bus CS1 Read Pre-Charge insert bit
After reading the CS1 space data, you can insert the unprocessed state for one clock. This bit determines whether the process is enabled or disabled. 1 means valid, 0 means invalid. This bit does not affect the operation after writing. See Figure 3.28 for the operation when this bit is set.