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External wait valid bit in CS1 space (19 [bit 12] in Figure 3.24)
A1EWT (W) A-Bus CS1 External WaiT effective bit
When accessing the CS1 space via A-Bus, a wait can be forced by an external signal, but this bit determines whether to enable or disable the processing. 1 means valid, 0 means invalid. When enabled, it continues to wait while the external signal is low. Refer to Figure 3.29 for the timing chart difference between when the external wait is invalid and when it is valid.

CS1 space burst cycle wait number setting bits (20 to 23 [bit 11 to 8] in Figure 3.24)
A1BW3-0 (W) A-Bus CS1 Burst sycle Wait bit3-0
Set the number of waits per cycle when performing burst access in CS1 space. Table 3.14 shows the setting values.

Table 3.14 CS1 space burst cycle setting values ​​ 
 0  
 0  
 0  
 1  
 bits 
 Number of waits 
A1BW3
A1BW2
A1BW1
A1BW0
0
0
0
 
 Do not wait (do not sample weight) 
0
0
0
 
 1 cycle wait 
: 
: 
: 
: 
 
1
1
1
 
 14 cycle wait 
1
1
1
 
 15 cycle wait

CS1 space normal cycle wait number setting bits (24 to 27 [bit 7 to 4] in Figure 3.24)
A1NW3-0 (W) A-Bus CS1 Normal cycle Wait bit3-0
Set the number of waits for one cycle when performing normal access in CS1 space. Table 3.15 shows the setting values.

Table 3.15 CS1 space normal cycle settings 
 0  
 0  
 0  
 1  
 bits 
 Number of waits 
A1NW3
A1NW2
A1NW1
A1NW0
0
0
0
 
 Do not wait (do not sample weight) 
0
0
0
 
 1 cycle wait 
: 
: 
: 
: 
 
1
1
1
 
 14 cycle wait 
1
1
1
 
 15 cycle wait

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