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CS1 space burst length setting bits (28 to 29 [bit 3 to 2] in Figure 3.24)
A1LN1-0 (W) A-Bus CS1 burst LeNgth bit1-0
Specify the access length (boundary) for burst access in CS1 space. Table 3.16 shows the length setting values.

Table 3.16 CS1 space burst length setting value 
 bit 
 access setting value 
A1LN1
A1LN0
 0 
 0 
 No burst access 
 0 
 1 
 4-address burst access 
 1 
 0 
 256 address burst access 
 1 
 1 
 No border

CS1 space bus size setting bit (Fig. 3.24, 30 [bit 0])
A1SZ (W) A-Bus CS1 bus SiZe bit
Set the A-Bus bus size in CS1 space. Table 3.17 shows the setting values.

Table 3.17 CS1 space bus size setting value 
 A1SZ 
 Bus size setting 
 0 
 Specify 16 bit bus 
 1 
 Specify 8-bit bus

Read ahead effective bit of CS2 space (1 [bit 31] in Figure 3.25)
A2PRD (W) A-Bus CS2 Previous ReaD bit
This bit determines whether to enable or disable CS2 space data prefetch processing. Data read-ahead processing reduces the time from access start to data output. However, this is valid only for the data stored at the next address of the accessed data, and other addresses remain the same as normal addresses. This bit is 1 for valid and 0 for invalid. See Figure 3.25 for the effect when prefetching is enabled.

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