CS2 space post-write precharge insertion bit (2 [bit 30] in Figure 3.25) A2WPC (W) A-Bus CS2 after Write Pri-Charge insert bit
After writing the data to CS2 space, you can insert the unprocessed state for 1 clock. This bit determines whether the process is enabled or disabled. 1 means valid, 0 means invalid. This bit does not affect the operation after reading. Refer to Figure 3.27 for the operation when this bit is set.
CS2 space post-read precharge insertion bit (3 [bit 29] in Figure 3.25) A2RPC (W) A-Bus CS2 Read Pri-Charge insert bit
After reading the CS2 space data, you can insert the unprocessed state for one clock. This bit determines whether the process is enabled or disabled. 1 means valid, 0 means invalid. This bit does not affect the operation after writing. See Figure 3.28 for the operation when this bit is set.
CS2 space external wait valid bit (4 [bit 28] in Figure 3.25) A2EWT (W) A-Bus CS2 External WaiT effective bit
When accessing the CS2 space via A-Bus, a wait can be forced by an external signal, but this bit determines whether to enable or disable the processing. 1 means valid, 0 means invalid. When enabled, it continues to wait while the external signal is low. Refer to Figure 3.29 for the timing chart difference between when the external wait is invalid and when it is valid.
CS2 space burst length setting bits (5 to 6 [bits 19 to 18] in Figure 3.25) A2LN1-0 (W) A-Bus CS2 burst LeNgth bit1-0
Specify the access length (boundary) for burst access in CS2 space. Table 3.18 shows the length setting values.
Table 3.18 CS2 spatial burst length setting value
bit
access setting value
A2LN1
A2LN0
0
0
No burst access
0
1
4-address burst access
1
0
256 address burst access
1
1
No border
CS2 space bus size setting bit (7 [bit 16] in Figure 3.25) A2SZ (W) A-Bus CS2 bus SiZe bit
Set the A-Bus bus size in CS2 space. Table 3.19 shows the setting values.