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Table 3.19 CS2 space bus size settings 
 A2SZ 
 Bus size setting 
 0 
 Specify 16 bit bus 
 1 
 Specify 8-bit bus

Pre-read effective bit of spare space (8 [bit 15] in Figure 3.25)
A3PRD (W) A-Bus CS3 Previous ReaD bit
This bit determines whether to enable or disable data prefetch processing for the spare space. Data read-ahead processing reduces the time from access start to data output. However, this is valid only for the data stored at the next address of the accessed data, and other addresses remain the same as normal addresses. This bit is 1 for valid and 0 for invalid. See Figure 3.25 for the effect when prefetching is enabled.

Precharge insertion bit after write in spare space (9 [bit 14] in Figure 3.25)
A3WPC (W) A-Bus CS3 after Write Pri-Charge insert bit
After writing data to the spare space, you can insert the unprocessed state for 1 clock. This bit determines whether the process is enabled or disabled. 1 means valid, 0 means invalid. This bit does not affect the operation after reading. Refer to Figure 3.27 for the operation when this bit is set.

Precharge insertion bit after read of spare space (10 [bit 13] in Figure 3.25)
A3RPC (W) A-Bus CS3 Read Pri-Charge insert bit
After reading the spare space data, you can insert the unprocessed state for one clock. This bit determines whether the process is enabled or disabled. 1 means valid, 0 means invalid. This bit does not affect the operation after writing. See Figure 3.28 for the operation when this bit is set.

External weight valid bit in spare space (11 [bit 12] in Figure 3.25)
A3EWT (W) A-Bus CS3 External WaiT effective bit
When accessing the spare space via A-Bus, a wait can be forced by an external signal, but this bit determines whether to enable or disable the processing. 1 means valid, 0 means invalid. When enabled, it continues to wait while the external signal is low. Refer to Figure 3.29 for the timing chart difference between when the external wait is invalid and when it is valid.

Reserved space burst cycle wait number setting bits (12 to 15 [bit 11 to 8] in Figure 3.25)
A3BW3-0 (W) A-Bus CS3 Burst sycle Wait bit3-0
Set the number of waits for one cycle when performing burst access in the spare space. Table 3.20 shows the setting values.

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