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Spare space bus size setting bits (22 [bit 0] in Figure 3.25)
A3SZ (W) A-Bus CS3 bus SiZe bit
Set the A-Bus bus size in the spare space. Table 3.23 shows the setting values.

Table 3.23 Spare space bus size settings 
 A3SZ 
 Bus size setting 
 0 
 Specify 16 bit bus 
 1 
 Specify 8 bit bus

A-Bus refresh register

Figure 3.30 shows the details of the A-Bus refresh register.

Figure 3.30 A-Bus refresh register (register: AREF) initial value 00000000H

A-Bus refresh output enable bit (1 [bit 4] in Figure 3.30)
ARFEN (W) A-Bus ReFresh ENable bit
Enables A-Bus refresh cycle output. Specify 1 to enable, 0 to disable.

A-Bus refresh wait number setting bits (2 to 5 [bits 3 to 0] in Figure 3.30)
ARWT3-0 (W) A-Bus Refresh WaiT bit3-0
Set the number of waits for A-Bus refresh cycle. Table 3.24 shows the details.

Table 3.24 A-Bus refresh wait count 
 0  
 0  
 0  
 1  
 bit 
 Number of waits 
ARWT3
ARWT2
ARWT1
ARWT0
0
0
0
 
 Do not wait 
0
0
0
 
 1 cycle wait 
: 
: 
: 
: 
 
1
1
1
 
 14 cycle wait 
1
1
1
 
 15 cycle wait

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