SEGA SATURN DEVELOPER'S MANUAL

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DMA instruction execution

Explains the process of setting DMA controller registers from DSP and actually performing DMA transfer. DMA instructions are divided into the following two types according to the transfer direction (read / write).

(1) Data transfer from D0 bus to DSP
(2) Data transfer from DSP to D0 bus

● Data transfer from D0 bus to DSP

Set the DSP data RAM transfer start address and external memory transfer start address in the registers ([CT0-3] and [RA0]), and transfer is started by the DMA instruction. The instruction format up to the DMA instruction is as follows. For details, refer to Section 4.5 “Instruction”.

MOV SImm, [CT0]; DSP data RAM0 transfer start address set
MVI Imm, [RA0]; External memory transfer start address set
DMA D0, [MD0], SImm; Start DMA transfer using D0 bus

Table 4.6 summarizes the features of this DMA transfer. Since DMA transfer is performed in units of 1 longword, the transfer word count setting (SImm for DMA instruction above) must be set in units of longwords.

Table 4.6 Features of data transfer from D0 bus to DSP

Item

Special

Set
flag

The TO flag of the program control port is set.

Start and Exit

Follow the data ready signal from the outside. By this signal, data is transferred
in units of one long word. The DMA transfer is terminated by an external end signal, and the TO flag of the program control port is reset at this timing.

Address Update

Every 1 longword transfer, DSP data RAM transfer address ([CTO-3]) is 1 is added, and the external memory transfer address ([RA0]) is added according to the address addition number.

Hold state

Setting the Hold bit of the DMA instruction (see section 4.5 “Instruction” DMA instruction) to 1
The number of transfer words ([TN0]) and the external memory transfer address ([RA0]) are retained at the time of transfer start.

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Item	Special
Set flag	The TO flag of the program control port is set.
Start and Exit	Follow the data ready signal from the outside. By this signal, data is transferred in units of one long word. The DMA transfer is terminated by an external end signal, and the TO flag of the program control port is reset at this timing.
Address Update	Every 1 longword transfer, DSP data RAM transfer address ([CTO-3]) is 1 is added, and the external memory transfer address ([RA0]) is added according to the address addition number.
Hold state	Setting the Hold bit of the DMA instruction (see section 4.5 “Instruction” DMA instruction) to 1 The number of transfer words ([TN0]) and the external memory transfer address ([RA0]) are retained at the time of transfer start.