A-Bus interrupt acknowledge output enable bit (= 0: disabled / = 1: enabled)  

 A-Bus refresh output enable bit (= 0: Invalid / = 1: Valid)  

 CS0 space, external wait valid bit (= 0: invalid / = 1: valid)  

 CS0 space, prefetch valid bit (= 0: invalid / = 1: valid)  

 CS0 space, post-read precharge insertion bit  

 CS0 space, bus size setting bit  

 CS0 space, post-write precharge insertion bit  

 CS1 space, external wait valid bit (= 0: invalid / = 1: valid)  

 CS1 space, prefetch valid bit (= 0: invalid / = 1: valid)  

 CS1 space, precharge insertion bit after read  

 CS1 space, bus size setting bit  

 CS1 space, post-write precharge insertion bit  

 CS2 space, external wait valid bit (= 0: invalid / = 1: valid)  

 CS2 space, prefetch valid bit (= 0: invalid / = 1: valid)  

 CS2 space, precharge insertion bit after read  

 CS2 space, bus size setting bit  

 CS2 space, post-write precharge insertion bit  

 Preliminary space, external wait valid bit (= 0: Invalid / = 1: Valid)  

 Preliminary space, prefetch valid bit (= 0: Invalid / = 1: Valid)  

 Pre-space, post-read precharge insertion bit  

 Preliminary space, bus size setting bit  

 Preliminary space, post-write precharge insertion bit  

 DSP program control port, carry flag  

 DMA A-Bus access flag (= 0: non-access / = 1: access)  

 DMA B-Bus access flag (= 0: non-access / = 1: access)  

 DMA DSP-Bus access flag (= 0: non-access / = 1: access)  

 DSP side DMA operation flag (= 0: Stop / = 1: Operation)  

 DSP side DMA waiting flag (= 0: Stop / = 1: Wait)  

 DMA forced stop bit (= 0: DMA operation enabled / = 1: DMA forced stop)  

 DMA Level 0 Interruption Flag (= 0: Stop / = 1: Interrupt)  

 DMA level 0 enable bit (= 0: Disable / = 1: Enable)