Return to previous page ｜ Return to menu ｜ Go to next page 

 DMA level 0 start bit (= 0: stop / = 1: start)  
 DMA level 0 mode bit (= 0: direct mode / = 1: indirect mode)  
 DMA level 0 operating flag (= 0: Stop / = 1: Operation)  
 DMA Level 0 Read Address Addition Value (= 0: Do not add / = 1: Add 4 bytes)  
 DMA level 0 read address update bit  
 DMA level 0 waiting flag (= 0: Stop / = 1: Wait)  
 DMA level 0 write address update bit  
 DMA Level 1 Interruption Flag (= 0: Stop / = 1: Interrupt)  
 DMA level 1 enable bit (= 0: Disable / = 1: Enable)  
 DMA level 1 start bit (= 0: stop / = 1: start)  
 DMA level 1 mode bit (= 0: direct mode / = 1: indirect mode)  
 DMA level 1 operating flag (= 0: Stop / = 1: Operation)  
 DMA level 1 read address addition value (= 0: Do not add / = 1: Add 4 bytes)  
 DMA level 1 read address update bit  
 abbreviation 
 address 
 bit 
 Contents 
D0FT2-0
25FE0014H
2-0
DMA level 0 activation factor selection bit 
 = 000B: V-blank-IN reception and enable bit set 
 = 001B: V-blank-OUT reception and enable bit set 
 = 010B: H-blank-IN Reception and permission bit set 
 = 011B: Timer 0 reception and permission bit set 
 = 100B: Timer 1 reception and permission bit set 
 = 101B: Sound Req reception and permission bit set 
 = 110B: Sprite drawing end and permission bit set 
 = 111B: DMA start bit set and permission bit set 
D0GO
25FE0010H
0
D0MOD
25FE0014H
24
D0MV
25FE007CH
4
D0RA
25FE000CH
8
D0RUP
25FE0014H
16
D0R26-0
25FE0000H
26-0
 
 DMA level 0 read address 
D0WA2-0
25FE000CH
2-0
 
 DMA level 0 write address addition value 
 = 000B: No addition 
 = 001B: 2Byte addition 
 = 010B: 4Byte addition 
 = 011B: 8Byte addition 
 = 100B: 16Byte addition 
 = 101B: 32Byte addition 
 = 110B: 64Byte addition 
 = 111B: 128Byte addition 
D0WT
25FE007CH
5
D0WUP
25FE0014H
8
D0W26-0
25FE0004H
26-0
 
 DMA level 0 write address 
D1BK
25FE007CH
17
D1C11-0
25FE0028H
11-0
 
 DMA level 1 transfer byte count 
D1EN
25FE0030H
8
D1FT2-0
25FE0034H
2-0
 
 DMA level 1 activation factor selection bit 
 = 000B: V-blank-IN reception and enable bit set 
 = 001B: V-blank-OUT reception and enable Bit set 
 = 010B: H-blank-IN reception and permission bit set 
 = 011B: Timer 0 reception and permission bit set 
 = 100B: Timer 1 reception and permission bit set 
 = 101B: Sound Req reception and permission bit set 
 = 110B: Sprite drawing end and permission bit set 
 = 111B: DMA start bit set and permission bit set 
D1GO
25FE0030H
0
D1MOD
25FE0034H
24
D1MV
25FE007CH
8
D1RA
25FE002CH
8
D1RUP
25FE0034H
16
D1R26-0
25FE0020H
26-0
 
 DMA level 1 read address

Return to previous page ｜ Return to menu ｜ Go to next page