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■ Frame buffer
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- Two 2Mbit DRAMs are divided into two parts, a display frame buffer and a drawing frame buffer.
- Switching between the display frame buffer and drawing frame buffer functions immediately before the screen display period (DISP). After power-on or reset, frame buffer 0 becomes the drawing frame buffer and frame buffer 1 becomes the display frame buffer.
- Read / write access from the syscon (system controller IC) to the frame buffer is performed only for the drawing frame buffer. The display frame buffer is a back bank and cannot be accessed.
- Drawing is performed in synchronization with the CPU operating clock. The CPU operating clock is 28MHz, and 1 pixel data is drawn synchronously.
- Read / write access from the syscon to the frame buffer and drawing access from VDP1 are given priority.
- Frame buffer access priority is always
Syscon> Draw
The order.
- During drawing, if you access it from syscon, drawing will be interrupted and wait, so avoid it as much as possible.
- To avoid drawing and CPU access at the same time, use a method such as setting the drawing start to manual start.
- Word access is possible for access. Byte access is possible when the display is 8bit / pixel (high resolution or rotation 8). Do not use byte access for 16bit / pixel.
- By reading the frame buffer diagonally, the entire frame buffer can be rotated. The entire frame buffer plane can be enlarged or reduced by skipping or repeating the address to be read. Rotation and enlargement / reduction can be performed simultaneously.
- The rotation is instructed by VDP2. Refer to the VDP2 manual for details on the rotation instructions.
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