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4.6 Transfer end status register

The transfer end status register (EDSR, End status register) indicates the end status of the previous frame processing. This is a read-only 16-bit register at address 100010H. Set unused bits to 0.

End bit fetch status in current frame: current end-bit fetch status (CEF), bit 1
Indicates whether the end bit (drawing end command) has been fetched from the command table in the current drawing frame. When it is 0, the end bit indicates an unfetched state, and when it is 1, it indicates that the end bit has been fetched and drawing has ended.

 CEF 
 End bit fetch status 
 0 
 End bit unfetched in current frame 
 1 
 End bit fetch and rendering end in current frame 


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