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● Drawing forced termination register

Transfer end status register

End bit fetch status in current frame: current end-bit fetch status (CEF), bit 1

 CEF 
 End bit fetch status 
 0 
 End bit unfetched in current frame 
 1 
 End bit fetching and rendering in the current frame: End of drawing: 

End bit fetch status in previous frame: before end-bit fetch status (BEF), bit 0

 BEF 
 End bit fetch status 
 0 
 End bit unfetched in previous frame 
 1 
 End bit fetching and drawing end in the previous frame 

Processing interruption table address register

Process interruption table address: Bits 15 to 0

● Current processing table address register

Current processing table address: Bits 15 to 0


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