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Table 2.3 H counter register bit contents 
 Graphic 
 Mode 
 HCT9 
HCT8
HCT7
HCT6
HCT5
HCT4
HCT3
HCT2
HCT1
HCT0
 Normal 
 H8 
 H7 
H6
H5
H4
H3
H2
H1
 
 H0 
 Disable 
 High Resolution 
 H9 
 H8 
H7
H6
H5
H4
H3
H2
H1
H0
 Dedicated Normal 
 Disable 
 H8 
H7
H6
H5
H4
H3
H2
H1
H0
 High Resolution 
 Disable 
 H9 
H8
H7
H6
H5
H4
H3
H2
H1

V counter register

V counter register indicates the V counter value. This is a read-only 16-bit register located at 18000AH.

V counter value bit : V counter bit (VCT9 to VCT0), bits 9 to 0

This signal is controlled by EXLTEN of the external signal enable register and represents the value of the latched V counter. The bit configuration of this register varies depending on the TV screen mode setting, as shown in Table 2.4. The V counter value in the normal and high-resolution mode single interlace indicates the V counter value in each field of even and odd fields. In normal and high-resolution mode double-density interlace, the V counter value indicates an odd field when the least significant bit VCT0 is 0, and an even field when it is 1, and VCT1 to VCT9 are V counters in the respective fields. Represents a value.

Table 2.4 V counter register bit contents 
 TV screen (interlace) mode 
 VCT9 
VCT8
VCT7
VCT6
VCT5
VCT4
VCT3
VCT2
VCT1
VCT0
 Normal, High-Res (Non-In 
 Tarace, Single Interlace) 
 V8 
V7
V6
V5
V4
V3
V2
 V1 
 V0 
 Disable 
 Normal, Hi-Res, (Double Dense 
 Tarace) 
 V8 
V7
V6
V5
V4
V3
V2
 V1 
 V0 
 0: odd 
 1: even 
 Dedicated Monitor 
 V9 
 V8 
V7
V6
V5
V4
V3
V2
V1
V0

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