∙ There are the following 10 types of VRAM access performed during one cycle.

(1) Normal scroll screen pattern name data read access
(2) Character pattern data read access for normal scroll screen
Or Bitmap pattern data read access
(3) NBG0, NBG1 vertical cell scroll table data read access
(4) Read / write access by CPU
(5) Do not access
(6) RBG0 pattern name data read access
(7) RBG0 character pattern data read access
Or Bitmap pattern data read access
(8) RBG0 coefficient table data read access
(9) RBG1 pattern name data read access
(10) RBG1 character pattern data read access

For VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1, each VRAM-A0, VRAM-A1, VRAM-B0, and VRAM-B1 must be specified for the VRAM access (1) to (5) above. Hmm. This is done by writing a 4-bit value called an access command corresponding to each VRAM access type to the VRAM cycle pattern register.
(VRAM access of (6) to (8) occupies all the timing of one cycle, so only one type can be specified for one bank. This is done by writing the value corresponding to each VRAM access type to the rotation data bank specification bit of the RAM control register. The VRAM cycle pattern register settings for the bank specified for VRAM access (6) to (8) are invalid.
(9) and (10) VRAM accesses occupy all the timing of one cycle, (9) is fixed to VRAM-B1, and (10) is fixed to VRAM-B0. (9), (10) is specified by