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Table 3.5 shows the access commands corresponding to the contents of VRAM access performed in one cycle.

Table 3.5 Access commands 
VCPnxx0
 
 0  
 1  
 0  
 1  
 0  
 1  
 0  
 1  
 0  
 1  
 0  
 1  
 0  
 1  
 0  
 1  
 Access command value 
 VRAM access contents 
VCPnxx3
VCPnxx2
VCPnxx1
0
0
0
 
 Read pattern name data for NBG0 
0
0
0
 
 Read pattern name data for NBG1 
0
0
1
 
 Read pattern name data for NBG2 
0
0
1
 
 Read pattern name data for NBG3 
0
1
0
 
 Character pattern data read for NBG0 
0
1
0
 
 Character pattern data read for NBG1 
0
1
1
 
 Character pattern data read for NBG2 
0
1
1
 
 Character pattern data read for NBG3 
1
0
0
 
 Prohibit setting 
1
0
0
 
 Prohibit setting 
1
0
1
 
 Prohibit setting 
1
0
1
 
 Prohibit setting 
1
1
0
 
 Read vertical cell scroll table data for NBG0 
1
1
0
 
 Read vertical cell scroll table data for NBG1 
1
1
1
 
 CPU read / write 
1
1
1
 
 No access
[Note] n: 0-7 (corresponding to access timing T0-T7)
xx: A0, A1, B0, B1 (VRAM-A0, VRAM-A1, VRAM-B0, VRAM- B1)

VRAM cycle pattern (for VRAM-A0) bit: VRAM cycle pattern bit
(VCP0A00 to VCP0A03, VCP1A00 to VCP1A03, VCP2A00 to VCP2A03, VCP3A00 to VCP3A03, VCP4A00 ​​to VCP4A03, VCP5A00 to VCP5A03, VCP6A00 to VCP6A03, VCP7A00 to VCP7 Set the access command for VRAM access to be performed at timing T0 to T7 of VRAM-A0 (or VRAM-A).

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