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 VCP0B00 to VCP0B03 
 180018H 
 bits 12-15 
 VRAM-B0 (or VRAM-B) timing T0 
 VCP1B00 to VCP1B03 
 180018H 
 bits 8 to 11 
 VRAM-B0 (or VRAM-B) timing T1 
 VCP2B00 to VCP2B03 
 180018H 
 bits 4 to 7 
 VRAM-B0 (or VRAM-B) timing T2 
 VCP3B00 to VCP3B03 
 180018H 
 bits 0 to 3 
 VRAM-B0 (or VRAM-B) timing T3 
 VCP4B00 to VCP4B03 
 18001AH 
 bits 12 to 15 
 VRAM-B0 (or VRAM-B) timing T4 
 VCP5B00 to VCP5B03 
 18001AH 
 bits 8 to 11 
 VRAM-B0 (or VRAM-B) timing T5 
 VCP6B00 to VCP6B03 
 18001AH 
 bits 4 to 7 
 VRAM-B0 (or VRAM-B) timing T6 
 VCP7B00 to VCP7B03 
 18001AH 
 bits 0 to 3 
 VRAM-B0 (or VRAM-B) timing T7 

VRAM cycle pattern (for VRAM-B1) bit: VRAM cycle pattern bit
(VCP0B10 to VCP0B13, VCP1B10 to VCP1B13, VCP2B10 to VCP2B13, VCP3B10 to VCP3B13, VCP4B10 to VCP4B13, VCP5B10 to VCP5B13, VCP6B10 to VCP6B13, VCP7B10 to VCPB Set the access command for VRAM access to be performed at timing T0 to T7 of VRAM-B1.

 VCP0B10 to VCP0B13 
 18001CH 
 bits 12-15 
 VRAM-B1 timing T0 
 VCP1B10 to VCP1B13 
 18001CH 
 bits 8 to 11 
 VRAM-B1 timing T1 
 VCP2B10 to VCP2B13 
 18001CH 
 bits 4 to 7 
 VRAM-B1 timing T2 
 VCP3B10 to VCP3B13 
 18001CH 
 bits 0 to 3 
 VRAM-B1 timing T3 
 VCP4B10 to VCP4B13 
 18001EH 
 bits 12 to 15 
 VRAM-B1 timing T4 
 VCP5B10 to VCP5B13 
 18001EH 
 bits 8 to 11 
 VRAM-B1 timing T5 
 VCP6B10 to VCP6B13 
 18001EH 
 bits 4 to 7 
 VRAM-B1 timing T6 
 VCP7B10 to VCP7B13 
 18001EH 
 bits 0 to 3 
 VRAM-B1 timing T7 

* If the VRAM is not divided into two, the value of this register is ignored.


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