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Table 4.8 Address value of map specification register by setting
Plain size Pattern name
Data size
Character size Bits used and actual
address value
1 horizontal page x 1 vertical page 1 word 1 horizontal cell × 1 vertical cell (value of bits 6 to 0) × 2000H
2 horizontal cells x 2 vertical cells (value of bits 8 to 0) × 800H
2 words 1 horizontal cell x 1 vertical cell (bits 5 to 0 Value) x 4000H
2 horizontal cells x 2 vertical cells (value of bits 7 to 0) × 1000H
2 horizontal pages x 1 vertical page 1 word 1 horizontal cell × 1 vertical cell (value of bits 6 to 1) × 4000H
2 horizontal cells x 2 vertical cells (value of bits 8 to 1) × 1000H
2 words 1 horizontal cell x 1 vertical cell (bits 5 to 1 Value) x 8000H
2 horizontal cells x 2 vertical cells (value of bits 7 to 1) × 2000H
2 horizontal pages x 2 vertical pages 1 word 1 cell horizontally × vertical 1 cell (value of bits 6 and 2) × 8000H
2 horizontal cells x 2 vertical cells (value of bits 8 to 2) × 2000H
2 words 1 horizontal cell x 1 vertical cell (bits 5 and 2 Value) x 10000H
2 horizontal cells x 2 vertical cells (value of bits 7 to 2) x 4000H
[Note] When VRAM capacity is set to 4M bits, the most significant bit in the used bits is not used.


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