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Specify the V counter value in each field of
and odd fields. In normal and high-resolution mode double-dense interlace, the least significant bit is invalid and the remaining bits specify the V counter value in each field.
∙ Table 8.2 shows the bit contents of the window position register depending on the screen mode setting.

Table 8.2 Bit contents of vertical position window position register
TV screen (interlaced)
Mode 		WxxY8 WxxY7WxxY6WxxY5WxxY4WxxY3WxxY2WxxY1WxxY0
Normal, High-Res
(Non-interlace,
Single-dense interlace) 		V8 V7 V6V5V4V3V2V1V0
Normal, High-Res
(Double Dense Interlace) 		V7 V6 V5V4V3V2 V1 V0 Disabled
Dedicated Monitor V8 V7 V6 V5V4V3V2V1V0
[Note] The bit name xx contains 0S, 0E, 1S, or 1E.

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