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V counter value bit : V counter bit (VCT9 to VCT0), bits 9 to 0
This signal is controlled by EXLTEN of the external signal enable register and represents the value of the latched V counter. 

 TV screen (interlace) mode 
 VCT9 
VCT8
VCT7
VCT6
VCT5
VCT4
VCT3
VCT2
VCT1
VCT0
 Normal, Hi-Res (Non-Italy, Single Dense) 
 V8 
V7
V6
V5
V4
V3
V2
 V1 
 V0 
 Disable 
 Normal, high resolution, (double dense 
 interlace) 
 V8 
V7
V6
V5
V4
V3
V2
 V1 
 V0 
 0: odd 
 1: even 
 Dedicated Monitor 
 V9 
 V8 
V7
V6
V5
V4
V3
V2
V1
V0

RAM control (Readable)

Color RAM coefficient table enable bit : Color RAM coefficient table enable bit (CRKTE), bit 15

Specify whether to store the coefficient table in color RAM. 

 CRKTE 
 Processing 
 0 
 Store coefficient table in VRAM 
 1 
 Store coefficient table in color RAM

Color RAM mode bits : Color RAM mode bits (CRMD1, CRMD0), bits 13, 12
Specify the color RAM mode. 

 RGB each with 5 bits, 1024 colors setting  
 RGB each with 5 bits and 2048 colors  
 RGB each set to 1024 colors  
 Prohibit setting 

CRMD1
CRMD0
 
 Mode 
 Processing 
0
0
0
0
1
1
1
0
2
1
1
−

VRAM mode bits : VRAM mode bits (VRBMD, VRAMD), bits 9, 8
Controls bank division of VRAM.

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