VCP0B10 to VCP0B13	18001CH	bits 12-15	VRAM-B1 timing T0
VCP1B10 to VCP1B13	18001CH	bit 8 ~ 11	VRAM-B1 timing T1
VCP2B10 to VCP2B13	18001CH	bit 4 ~ 7	VRAM-B1 timing T2
VCP3B10 to VCP3B13	18001CH	bit 0 ~ 3	VRAM-B1 timing T3
VCP4B10 to VCP4B13	18001EH	bit 12 ~ 15	VRAM-B1 timing T4
VCP5B10 to VCP5B13	18001EH	bit 8 ~ 11	VRAM-B1 timing T5
VCP6B10 to VCP6B13	18001EH	bit 4 ~ 7	VRAM-B1 timing T6
VCP7B10 to VCP7B13	18001EH	bit 0 ~ 3	VRAM-B1 timing T7

VCPnxx0

 0  

 1  

 0  

 1  

 0  

 1  

 0  

 1  

 0  

 1  

 0  

 1  

 0  

 1  

 0  

 1  

Access command value				VRAM access contents
VCPnxx3	VCPnxx2	VCPnxx1
0	0	0	Read pattern name data for NBG0
0	0	0	Read pattern name data for NBG1
0	0	1	Read pattern name data for NBG2
0	0	1	Read pattern name data for NBG3
0	1	0	Character pattern data read for NBG0
0	1	0	Character pattern data read for NBG1
0	1	1	Character pattern data read for NBG2
0	1	1	Character pattern data read for NBG3
1	0	0	Prohibit setting
1	0	0	Prohibit setting
1	0	1	Prohibit setting
1	0	1	Prohibit setting
1	1	0	Read vertical cell scroll table data for NBG0
1	1	0	Read vertical cell scroll table data for NBG1
1	1	1	CPU read / write
1	1	1	No access

[Note] n: 0-7 (corresponding to access timing T0-T7) xx: A0, A1, B0, B1 (VRAM-A0, VRAM-A1, VRAM-B0, VRAM- B1)