CPU clock 26MHz ← → 28MHz
Horizontal resolution 320/640 ← → 352/704 

System clock switching involves a reset to some hardware.

Device to be reset .	OFF or no warranty device	Unaffected device
SCU VDP1 VDP2 SCSI / SCC (development only)	Slave SH (OFF ) DRAM (Destruction of previous contents) SCSP (OFF)	Master SH * Note SDRAM CD SIMM (development machine only)
* Note: Since master SH is in standby mode during clock switching, : FRT and SCI among SH built-in modules must be reset Nina WDT is used in this process. Also, after processing, there is an NMI, for example, the DMAC control role is suspended by the NMI. Refer to the SH manual and perform processing to resume processing if necessary.

  Re-initialization after reset:  

SCU ………… Re-initialize bus, interrupt mask, etc. However, the SYS_GETSCUIM value is used as the interrupt mask value. 

 Post-processing required by the application:  

VDP2 ……………… You need to set TV mode relatively quickly. The device itself is in 320/640 mode after reset
Since this will be a synchronization signal to the TV, especially when the system clock is changed to 352/704 mode.
The screen is misaligned and the screen may be distorted. 

VDP1, 2, SCSP …… All previous settings are invalid. Reconfiguration is required. 

SMPC: Hot reset is always enabled (permitted). 

The clock change processing time is approximately 110 ms.
This is because it includes device reset time.