Table 3.3 Bit configuration of interrupt factor register

5

PEND

Register name	R / W	15	14	13	12	11	10	9	8
HIRQREQ	R/W	−	-	MPST	MPCM	MPED	SCDQ	EFLS	ECPY
		7	6	4	3	2	1	0
		EHST	ESEL	DCHG	BFUL	CSCT	DRDY	CMOK

bit	Name	Description	initial value
bit0	CMOK	1: Command can be issued (Response Set complete)	1
bit1	DRDY	1: Ready for data transfer	0
bit2	CSCT	1: 1 sector read complete (1 sector read from CD-ROM is stored or erased in a partition)	0
bit3	BFUL	1: CD buffer full (CD Buffer is full)	0
bit4	PEND	1: End of CD playback ( Current FAD is out of playback range)	0
bit5	DCHG	1: Disk replacement occurred ( Tray opened)	0 *
bit6	ESEL	1: Soft reset, selector setting End of processing	1
bit7	EHST	1: Host I / O processing End	1
bit8	ECPY	1: Copy between buffer sections / End move process	1
bit9	EFLS	1: CD block file system processing End	1
bit10	SCDQ	1: Update subcode Q Complete (CD drive communication timing)	0
bit11	MPED	1: End of MPEG-related processing	1
bit12	MPCM	1: MPEG operation indefinite interval End	0
bit13	MPST	1: MPEG interrupt status notification (MPEG related interrupt occurred)	0
bit14	-	reserved bit	0
bit15	-	reserved bit	0

 * DCHG = 1 at hard reset, but 0 is cleared in BOOT ROM.
∙ DCHG is not initialized at software reset. (CDC function writes 0BE1H)
As a rule, DCHG clears BOOT ROM to 0 when checking the disk. 

(A) Only 0 (clear) can be written to the bit.
(B) IRQ output to the host is an OR output of all factors.
* Clear the corresponding factor bit during interrupt processing.
(C) The ESEL, EHST, ECPY, EFLS, and MPED bits are collectively called the command end flag.
Notify the end of execution of commands belonging to each flag.
The initial value of the (d) bit is 1 for CMOK and the command end flag, and 0 for others.
(Initial value bit pattern: 0BC1H)
Actually, the bits other than 1 are undefined, so the CDC function is cleared to 0.