Table 3.4 Bit structure of interrupt register
Register name | R / W | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
HIRQMSK | R/W | − | - | MPST | MPCM | MPED | SCDQ | EFLS | ECPY |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
EHST | ESEL | DCHG | BFUL | CSCT | DRDY | CMOK |
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(A) The meaning of the bit is the same as the interrupt factor register.
(1: Interrupt enabled, 0: Mask)
(B) When an interrupt is masked, the following occurs when an interrupt signal is input.
· Not reflected in IRQ output.
• Reflected in the interrupt factor register. (Polling is possible)
(C) The initial value of each bit is 0. (Not initialized by soft reset)
Table 3.5 MPEG register bit configuration
Register name | R / W | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MPEGRGB | R | ||||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
Bit0 ~ bit15: RGB data (Please refer to the MPEG part for details)