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VRAM division and cycle pattern setting

VDP2 displays the scroll screen data while reading it from VRAM in synchronization with the TV scan. The VRAM access during the display period is repeated four times (high resolution screen) or eight times (normal screen) as the access operation unit (1 cycle).
Cycle cycle registers are provided for each VRAM and bank of VRAM A (VRAM A0, VRAM A1) and VRAM B (VRAM B0, VRAM B1). Access is represented by 4 bits per command.
(Please refer to “VDP2 User's Manual 3.4 How to access VRAM during display period”)
The number of accesses set in the cycle pattern varies depending on the data type and usage method. These must be assigned to the cycle pattern table.

Table 1. Number of pattern name table data accesses required for one cycle 
 Item 
 NBG0 to NBG3 
RBG0 , RBG1
 
 Reduction settings 
 1x 
 1/2 times 
 1/4 times 
 − 
 Number of VRAM accesses required for one cycle 
 1 
 2
4
8

Table 2 Character pattern data (bitmap pattern data) data access count 

 Item 
 NBG0 to NBG3 
RBG0 , RBG1
 
 TV screen mode 
 
 
 
 
 
 Normal 
 High Resolution 
 Only 
 Number of characters 
 16 
256
2048
32768
167710,000 
-
 
-
 
-
 
 Reduce (Double) 
 1 
 1/2 
1/4
1
1/2
1
1
1
 
-
 
-
 
-
 
 Number of VRAM accesses required for one cycle 
 1 
 2
4
2
4
4
4
8
8
4
4

For example, in the case of 16-color bitmap data (handled as character pattern data), four 512x256 data can be placed in either VRAM A or VRAM B alone. If this is assigned to each normal scroll surface, the total number of accesses will be 4. However, NBG0 and NBG1 on the normal scroll surface have a reduction function. If you use this function and set the 1/4 reduction setting for each, the total number of accesses will be 10 times, exceeding 8 times, and will not be displayed correctly on the screen. In that case, if the VRAM is divided, the number of accesses will be distributed, so it will be displayed correctly on the screen.

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