drcr / * DMA request / response selection control * / 

Constant	Description
DMA_CPU_DREQ	DREQ (external request)
DMA_CPU_RXI	RXI (Built-in SCI receive data full interrupt transfer request)
DMA_CPU_TXI	TXI (Built-in SCI transmit data empty interrupt Transfer request)

 msk / * Mask bit * / 

Member write mask bits. The bits specified by the following constants are not written (set). Multiple specification by logical sum is possible.

Constant	Description
DMA_CPU_M_SAR	DMA source address
DMA_CPU_M_DAR	DMA destination address
DMA_CPU_M_TCR	DMA transfer count
DMA_CPU_M_DM	Destination address mode
DMA_CPU_M_SM	Source address mode bits
DMA_CPU_M_TS	Transfer size
DMA_CPU_M_AR	Auto request mode
DMA_CPU_M_IE	Interrupt enable
DMA_CPU_M_DRCR	DMA request / response selection control
DMA_CPU_M_TE	Transfer end flag