DMA

Transfer from A-BUS to C-BUS using CPU-DMA does not work.

Q)

I am using CPU DMA to transfer from ABUS to CBUS (work RAM-L), but it seems that the second and subsequent transfers are failing.
The number of transfers obtained by CDC_DATAEnd returns a normal value for the first transfer, but for the second and subsequent transfers, a value of 5 words is always returned, and not a single byte has been transferred to the transfer destination.
The routine is described below, but is any processing required before the transfer?

A)

Add DMA_CPU_M_TE to DmaC.msk, a parameter passed to the DMA_CpuSetPrm function.
Detail is,

SH7095 Hardware Manual Chapter 9 Direct Memory Access Controller 9.2.4 DMA Channel Control Registers 0, 1

Please refer to.

Transfer between the same buses is not possible using SCU-DMA.

Q)

DMA_ScuMemCopy() does not work properly when copying between WORK_RAM_Hs.
What reasons can you think of?

A)

SCU-DMA is a DMA that performs transfers between different buses.
This cannot be done in the same space.
Please use CPU-DMA or software transfer for data transfer in the same space.

＜ Transfer examples that can use SCU-DMA＞

WorkRAM-H ←→ VDP1
WorkRAM-H ─→ VDP2
WorkRAM-H ←→ SCSP(SoundRAM)
CD Buffer ─→ WorkRAM-H
CD Buffer ─→ VDP1
CD Buffer ─→ VDP2
CD Buffer ─→ SCSP(SoundRAM)

Transfer from HighRAM to B-Bus does not work with SCU-DMA.

Q)

I am trying to transfer data from work RAM-H to B-BUS using SCU DMA 2ch in indirect mode, but no data is transferred at all.
Please let me know what could be the cause.

A)

What are the SCU indirect mode table settings?
Please set "Number of bytes transferred", "Write address", and "Read address" in this order.

├──────────────────────┤
│ Number of bytes      │m ←Set in the write address register
│ transferred 1st time │
├──────────────────────┤ Address
│ First write address  │m+4
├──────────────────────┤ 
│ First read address   │m+8
├──────────────────────┤
│           :          │
│           :          │
│           :          │
│           :          │
├──────────────────────┤
│ Number of bytes      │
│ transferred nth time │
├──────────────────────┤
│ nth write address    │
├─┬────────────────────┤
│1│nth read address    │
└─┴────────────────────┘
 ↑
 Be sure to set "1" to the 31st bit of the nth read address. 

Regarding SCU-DMA indirect mode table specifications.

Q)

The SCU-DMA indirect mode table specifications state that if the table size is up to 1020 bytes, the start address is placed on the 1024-byte boundary, but what happens if the data exceeds 1020 bytes?
Currently it seems to be working on a 1024-byte boundary (the table is currently about 2688 bytes), but does this mean that it will not be guaranteed in the future?

A)

According to the SCU additional manual (No. 25), a data table of 2 ^ m bytes is required when the data size is up to (n x 12) bytes. In other words, the data size currently used there is ( 2 ^ 11 ) = 2048 < 2688 = ( 224 × 12 ) <= 2688 < 4096 = ( 2 ^ 12 ), so a table size of 4096 bytes is required. It becomes.

About the limitations during level 1 boot in DMA.

Q)

In SCU-DMA, there is a statement that DMA level 2 is prohibited from starting while DMA level 1 is being executed, but does this just prohibit starting DMA level 2 when DMA level 1 is operating (DMA transfer in progress)?

If DMA level 1 is automatically started by SCU interrupt, does that mean that level 1 is always active?

It says it's a malfunction, but what are the specific symptoms?
Is it okay to use it if it does not affect the game?

A)

This is prohibited.
If you start level 2 while running level 1, unexpected things will happen and normal operation cannot be guaranteed.
If you are using it, please change the program.

Regarding SCU-DMA simultaneous use channels.

Q)

The number of channels that can be used simultaneously with SCU-DMA is 2 channels, and if 3 channels are used simultaneously, the priority will be ignored. Does this mean that all 3 will always end just because the priority is ignored?

If priorities are ignored, what is the exact order?

Also, this overlaps with the previous question, but if the priority is ignored, if level 1 starts up while level 2 starts up, will malfunctions occur in that case?

A)

Please do not use this as it is prohibited by hardware.

Which is the fastest way to transfer from LowRAM to VDP1?

Q)

I would like to use the WORK_RAM_L area as a buffer for sprite data, but what is the fastest method to transfer from the WORK_RAM_L area to the SPR_VRAM area?
It seems that SCU_DMA cannot be used, so I would like to use CPU_DMA.

A)

The fastest way to transfer from the WORK_RAM_L area is to use CPU-DMA transfer, depending on the amount of transfer.
If the amount of transfer is small (several bytes), DMA transfer requires a wait of several clocks before and after startup, so memory transfer may be better.