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■3.2 SCU

The SCU smoothly interfaces multiple processors to the CPU-bus, A-bus, and B-bus. Furthermore, it is equipped with a DMA controller, interrupt controller, and DSP.

●System configuration
The SMPC is connected to the CPU-bus and controls the system reset signal and control pad.
Devices that supply programs, such as cartridges and CDs, are connected to the A-bus.
The SCU interrupt controller controls interrupts from A-bus, B-bus, and SMPC. It also supports timer interrupts and can generate an interrupt (INT signal) in synchronization with the screen display (Figure 3.1).

Figure 3.1 SCU system configuration

●System specifications
Table 3.2 SCU system specifications
No Item specification remarks
1
 DSP
・32bit×32bit → 48bit
・ 14MHz Note 1
・ Program RAM 32bit×256word
・ DATA RAM 32bit×64word×4 pieces
・ Includes DMA instructions


 2
 DMA
・3ch for CPU, 1ch for DSP
・ 3 levels, 1 stack set
・ Can be activated by interrupt
・ With indirect mode


 4
 interrupt control
・Timer (2ch) synchronized with the screen and
・ Controlling interrupts from external pins


 5
 A-bus control
・Bus sizing of A-bus (external bus)
・ weight control
・ Setting burst size
・ Refresh control


 6
 B-bus control
・B-bus (internal bus) control
・VDP1, VDP2, SCSP only





 ●Function
 The features of SCU are listed below.
 Data transfer between main CPU (SH-2), internal DSP, A-bus, and B-bus
 The SCU is equipped with a CPU I/F, A-bus I/F, and B-bus I/F, and can smoothly interface with multiple processors connected via each I/F and bus. I will do it. Furthermore, it is possible to transfer programs from the main CPU to the DSP inside the SCU. Additionally, while data is being transferred between the A-bus and B-bus, the CPU can access the work area using the CPU-bus, allowing processing to be executed using independent buses in parallel. Masu.
 interrupt control
 Interrupts that span other processors are issued via the SCU. For example, if you want to display the volume level on the screen, the SCSP generates an interrupt requesting the SCU to display the screen. Additionally, the SCU recognizes interrupts and causes them to be issued in synchronization with the screen. At this time, an interrupt can be issued at any point (dot) on the screen.
 Internal DSP
 The SCU is equipped with an internal DSP. This is provided to enable processing that would be difficult to implement due to the excessive load placed on the main CPU alone.
 Operating frequency
 The operating frequency of the DSP inside the SCU is 1/2 that of the main CPU. The relationship with the operating frequency of the main CPU is as follows.

 Table 3.2.1 SCU-DMA clock details

 Screen display mode SH-2 operating clock SCU-DSP operating clock


 In 320 dot mode (NTSC system)
 26.8741MHz
 13.4371MHz


 352 dot mode (NTSC system)
 28.6364MHz
 14.3182MHz


 In 320 dot mode (PAL system)
 26.6877MHz
 13.3439MHz


 352 dot mode (PAL system)
 28.4377MHz
 14.2189MHz







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★ HARDWARE Manual ★ SEGA Saturn Overview Manual


 Copyright SEGA ENTERPRISES, LTD., 1997