Chapter 3 SCSP function

■3.1 Interface

SCSP has two built-in CPU interfaces (main CPU and sound CPU).
The priority of the main CPU interface is higher, so the processing speed of the sound CPU depends on the operation of the main CPU.

●Sound CPU interface

The sound CPU interface is a block with specialized functions that allows you to connect a sound CPU. By providing this interface, the sound CPU can be connected to the SCSP without any external circuitry.
Sound CPU programs reside in sound memory. Therefore, all CPU programs are placed in the address space of the sound CPU.

●Main CPU interface

Figure 3.1 shows the access between the main CPU and the interface.

Figure 3.1 Access overview

The interface starts when the select signal (MCCSN) from the main CPU falls, and ends when the select signal rises. Also, when "1" is output to the ready signal (MCRDYN) to the main CPU, the select signal (MCCSN) from the main CPU and the main CPU data bus (MCD[7:0]) do not change.

●Notes on interfacing with the main CPU

• Read and write in 16-bit units (word units).
  → Access in 8-bit units (byte units) is not possible from the main CPU.

• When there is a read/write request, the address and data are loaded into the buffer within SCSP. As a result, "1" is output to the ready signal (MCRDYN) to the main CPU and a wait occurs. This wait continues until the LSI's internal processing is completed, so please avoid using continuous writes, which cause frequent waits, except when the power is turned on.

• When the power is turned on, the time required to initialize the sound memory by continuous writing is approximately 100msec with 4Mbit DRAM.

■3.2 Memory access control

When accessing sound memory from SCSP, the following priorities are maintained.

1. PCM data read by PCM sound source, access by DSP
2. DRAM refresh cycle
3. DMA transfer
4. Access by main CPU
5. Access by sound CPU

If there is a higher priority access request, weight is given to the lower priority access request. In addition, the decision as to which device memory access should be granted to a device requesting memory access (PCM sound source section, DSP section, main CPU, sound CPU, DMA, etc.) is made before the actual memory access is performed. has also been executed before, so a higher-ranked access request will not occur while a lower-ranked access request is being executed.

Figure 3.2 Memory access priority

SCSP/sound CPU performance is determined by memory cycle allocation.
Memory cycles are performed 128 times during one sample (1 / 44.1K≒22.68μsec), and these 128 cycles are distributed to each device. Since the number of CPU accesses varies depending on the application, there is no best method for memory access, but please note the following:

●Notes on memory access

• Sound memory uses DRAM, so a refresh cycle is required.
  Since the Saturn Sound System requires two free cycles between each sample, the number of memory cycles available to other devices is 126.

• The sound source and DSP memory cycles have the highest priority memory cycle.

• The sound source uses two memory cycles for each slot sound, so a total of 64 memory cycles are used for up to 32 slots.
  When the EG is in the maximum attenuation state ("3FFH"), the sound source does not access memory. Please set KEY_OFF for slots that do not output audio.

• The DSP performs up to 64 memory accesses. This depends on the DSP application. When you want to temporarily store data in a DSP, use registers inside the DSP as much as possible.

• When using SCSP's built-in DMA, a considerable amount of weight is placed on the sound CPU, which slows down the sound CPU.