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SCU User's Manual/Chapter 4 DSP Control Arithmetic instruction
Y-Bus control instructions
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NOP
- Operation details
- The Y-Bus instruction section will be unprocessed.
- descriptive formula
- label: NOP
- instruction code
31 | 30 | | | | | | |
| | | | 19 | 18 | 17 | |
| | | | | | | |
| | | | | | | 0 |
0 | 0 | − | − | − | − | − | − |
− | − | − | − | 0 | 0 | 0 | − |
− | − | − | − | − | − | − | − |
− | − | − | − | − | − | − | − |
- flag
- No change.
- remarks
- none.
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MOV[s],Y
- Operation details
- Data is transferred from the data RAM at the address indicated by [CTx(x=0 to 3)] to [RY].
- descriptive formula
- label: MOV[Source RAM],Y
- Source RAM=M0~M3,MC0~MC3
- instruction code
31 | 30 | | | | | | |
| | | | 19 | 18 | 17 | 16 |
15 | 14 | | | | | | |
| | | | | | | 0 |
0 | 0 | − | − | − | − | − | − |
− | − | − | − | 1 | 0 | 0 | x |
x | x | − | − | − | − | − | − |
− | − | − | − | − | − | − | − |
bit data | Addition mode options |
bit16 | bit15 | bit14 |
0 | 0 | 0 | DATA RAM0→[RY] |
0 | 0 | 1 | DATA RAM1→[RY] |
0 | 1 | 0 | DATA RAM2→[RY] |
0 | 1 | 1 | DATA RAM3→[RY] |
1 | 0 | 0 | DATA RAM0→[RY],CT0++ |
1 | 0 | 1 | DATA RAM1→[RY],CT1++ |
1 | 1 | 0 | DATA RAM2→[RY],CT2++ |
1 | 1 | 1 | DATA RAM3→[RY],CT3++ |
- flag
- RY;This will be the data selected in the options.
- CTx(x=0~3);Incremented only when b22=1. There is no change when b22=0.
- remarks
- [Mx(x=0~3)] specifies DATA RAMx(x0~3).
- [MCx(x=0~3)] specifies DATA RAMx(x0~3), and after transfer, increments [CTx(x=0~3)].
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CLR A
- Operation details
- Clear the [ACH] and [ACL] values to 0.
- descriptive formula
- label: CLR A
- instruction code
31 | 30 | | | | | | |
| | | | 19 | 18 | 17 | |
| | | | | | | |
| | | | | | | 0 |
0 | 0 | − | − | − | − | − | − |
− | − | − | − | 0 | 0 | 1 | − |
− | − | − | − | − | − | − | − |
− | − | − | − | − | − | − | − |
- flag
- ACH; becomes 0.
- ACL; becomes 0.
- remarks
- none.
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MOV ALU,A
- Operation details
- Transfer the value of the upper 16 bits of [ALU] to [ACH], and the value of the lower 32 bits of [ALU] to [ACL].
- descriptive formula
- label: MOV ALU,A
- instruction code
31 | 30 | | | | | | |
| | | | 19 | 18 | 17 | |
| | | | | | | |
| | | | | | | 0 |
0 | 0 | − | − | − | − | − | − |
− | − | − | − | 0 | 1 | 0 | − |
− | − | − | − | − | − | − | − |
− | − | − | − | − | − | − | − |
- flag
- ACH; This is the data of the upper 16 bits of ALU.
- This is the data of the lower 32 bits of ACL;ALU.
- remarks
- none.
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MOV[s],A
- Operation details
- Transfer data from the data RAM at the address indicated by [CTx(x=0 to 3)] to [ACL]. Also, the value of [ACH] changes with the sign extension of [ACL].
- descriptive formula
- label: MOV [Source RAM],A
- Source RAM = M0~M3,MC0~MC3
- instruction code
31 | 30 | | | | | | |
| | | | 19 | 18 | 17 | 16 |
15 | 14 | | | | | | |
| | | | | | | 0 |
0 | 0 | − | − | − | − | − | − |
− | − | − | − | 0 | 1 | 1 | x |
x | x | − | − | − | − | − | − |
− | − | − | − | − | − | − | − |
bit data | Addition mode options |
bit16 | bit15 | bit14 |
0 | 0 | 0 | DATA RAM0→[ACL] |
0 | 0 | 1 | DATA RAM1→[ACL] |
0 | 1 | 0 | DATA RAM2→[ACL] |
0 | 1 | 1 | DATA RAM3→[ACL] |
1 | 0 | 0 | DATA RAM0→[ACL],CT0++ |
1 | 0 | 1 | DATA RAM1→[ACL],CT1++ |
1 | 1 | 0 | DATA RAM2→[ACL],CT2++ |
1 | 1 | 1 | DATA RAM3→[ACL],CT3++ |
- flag
- ACL: This will be the data selected in the options.
- Changes with sign extension of ACH;[ACL].
- CTx(x=0~3);Incremented only when b16=1. There is no change when b16=0.
- remarks
- [Mx(x=0~3)] specifies DATA RAMx(x0~3).
- [MCx(x=0~3)] specifies DATA RAMx(x0~3), and after transfer, increments [CTx(x=0~3)].
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★ HARDWARE Manual ★ SCU User's Manual
Copyright SEGA ENTERPRISES, LTD., 1997