| Abbreviation | address | bit | Contents |
|---|---|---|---|
| AIACK | 25FE00A8H | 0 | A-Bus interrupt acknowledge output enable bit (=0: Disabled/=1: Enabled) |
| ARFEN | 25FE00B8H | 4 | A-Bus refresh output enable bit (=0: Disabled/=1: Enabled) |
| ARWT3-0 | 25FE00B8H | 3-0 | A-Bus refresh wait number |
| A0BW3-0 | 25FE00B0H | 27-24 | CS0 space, burst cycle wait number setting bit |
| A0EWT | 25FE00B0H | 28 | CS0 space, external wait valid bit (=0: invalid / =1: valid) |
| A0LN1-0 | 25FE00B0H | 19-18 | CS0 space, burst length setting bit |
| A0PRD | 25FE00B0H | 31 | CS0 space, look-ahead valid bit (=0: invalid / =1: valid) |
| A0RPC | 25FE00B0H | 29 | CS0 space, precharge insertion bit after read |
| A0NW3-0 | 25FE00B0H | 23-20 | CS0 space, normal cycle wait number setting bit |
| A0SZ | 25FE00B0H | 16 | CS0 space, bus size setting bit |
| A0WPC | 25FE00B0H | 30 | CS0 space, precharge insertion bit after write |
| A1BW3-0 | 25FE00B0H | 11-8 | CS1 space, burst cycle wait number setting bit |
| A1EWT | 25FE00B0H | 12 | CS1 space, external wait valid bit (=0: invalid / =1: valid) |
| A1LN1-0 | 25FE00B0H | 3-2 | CS1 space, burst length setting bit |
| A1NW3-0 | 25FE00B0H | 7-4 | CS1 space, normal cycle wait number setting bit |
| A1PRD | 25FE00B0H | 15 | CS1 space, look-ahead valid bit (=0: invalid / =1: valid) |
| A1RPC | 25FE00B0H | 13 | CS1 space, precharge insertion bit after read |
| A1SZ | 25FE00B0H | 0 | CS1 space, bus size setting bit |
| A1WPC | 25FE00B0H | 14 | CS1 space, precharge insertion bit after write |
| A2EWT | 25FE00B4H | 28 | CS2 space, external wait valid bit (=0: invalid / =1: valid) |
| A2LN1-0 | 25FE00B4H | 19-18 | CS2 space, burst length setting bit |
| A2PRD | 25FE00B4H | 31 | CS2 space, lookahead valid bit (=0: invalid / =1: valid) |
| A2RPC | 25FE00B4H | 29 | CS2 space, precharge insertion bit after read |
| A2SZ | 25FE00B4H | 16 | CS2 space, bus size setting bit |
| A2WPC | 25FE00B4H | 30 | CS2 space, precharge insertion bit after write |
| A3BW3-0 | 25FE00B4H | 11-8 | Spare space, burst cycle wait number setting bit |
| A3EWT | 25FE00B4H | 12 | Reserve space, external wait valid bit (=0: invalid / =1: valid) |
| A3LN1-0 | 25FE00B4H | 3-2 | Spare space, burst length setting bit |
| A3NW3-0 | 25FE00B4H | 7-4 | Spare space, normal cycle wait number setting bit |
| A3PRD | 25FE00B4H | 15 | Spare space, look-ahead valid bit (=0: invalid / =1: valid) |
| A3RPC | 25FE00B4H | 13 | Spare space, precharge insertion bit after read |
| A3SZ | 25FE00B4H | 0 | Spare space, bus size setting bit |
| A3WPC | 25FE00B4H | 14 | Spare space, precharge insertion bit after writing |
| C | 25FE0080H | 20 | DSP program control port, carry flag |
| DACSA | 25FE007CH | 20 | DMA A-Bus access flag (=0: no access/=1: access) |
| DACSB | 25FE007CH | 21 | DMA B-Bus access flag (=0: non-access/=1: access) |
| DACSD | 25FE007CH | 22 | DMA DSP-Bus access flag (=0: non-access/=1: access) |
| DDMV | 25FE007CH | 0 | DSP side DMA operation flag (=0: stopped/=1: operating) |
| D.D.W.T. | 25FE007CH | 1 | DSP side DMA standby flag (=0: Stop / =1: Wait) |
| DSTOP | 25FE0060H | 0 | DMA forced stop bit (=0: DMA operation enabled/=1: DMA forced stop) |
| D0BK | 25FE007CH | 16 | DMA level 0 suspended flag (=0: stopped/=1: interrupted) |
| D0C19-0 | 25FE0008H | 19-0 | DMA level 0 transfer byte count |
| D0EN | 25FE0010H | 8 | DMA level 0 permission bit (=0: Disable/=1: Enable) |
| D0FT2-0 | 25FE0014H | 2-0 | DMA level 0 activation factor selection bit =000B: V-blank-IN reception and permission bit set =001B: V-Blank-OUT reception and permission bit set =010B: H-Blank-IN reception and permission bit set =011B: Timer 0 reception and permission bit set =100B: Timer 1 reception and permission bit set =101B: Sound Req reception and permission bit set =110B: Sprite drawing end and permission bit set =111B: DMA activation bit set and permission bit set |
| D0GO | 25FE0010H | 0 | DMA level 0 start bit (=0: stop/=1: start) |
| D0MOD | 25FE0014H | 24 | DMA level 0 mode bit (=0: Direct mode/=1: Indirect mode) |
| D0MV | 25FE007CH | 4 | DMA level 0 operating flag (=0: stopped / = 1: operating) |
| D0RA | 25FE000CH | 8 | DMA level 0 read address addition value (=0: not added/=1: 4Byte addition) |
| D0RUP | 25FE0014H | 16 | DMA Level 0 Read Address Update Bit |
| D0R26-0 | 25FE0000H | 26-0 | DMA level 0 read address |
| D0WT | 25FE007CH | 5 | DMA level 0 standby flag (=0: stop / =1: standby) |
| D0WUP | 25FE0014H | 8 | DMA level 0 write address update bit |
| D0W26-0 | 25FE0004H | 26-0 | DMA level 0 write address |
| D1BK | 25FE007CH | 17 | DMA level 1 suspended flag (=0: stopped/=1: interrupted) |
| D1C11-0 | 25FE0028H | 11-0 | DMA level 1 transfer byte count |
| D1EN | 25FE0030H | 8 | DMA level 1 permission bit (=0: Disable/=1: Enable) |
| D1FT2-0 | 25FE0034H | 2-0 | DMA level 1 activation factor selection bit =000B: V-blank-IN reception and permission bit set =001B: V-Blank-OUT reception and permission bit set =010B: H-Blank-IN reception and permission bit set =011B: Timer 0 reception and permission bit set =100B: Timer 1 reception and permission bit set =101B: Sound Req reception and permission bit set =110B: Sprite drawing end and permission bit set =111B: DMA activation bit set and permission bit set |
| D1GO | 25FE0030H | 0 | DMA level 1 activation bit (=0: stop/=1: start) |
| D1MOD | 25FE0034H | 24 | DMA level 1 mode bit (=0: Direct mode/=1: Indirect mode) |
| D1MV | 25FE007CH | 8 | DMA level 1 operating flag (=0: stopped / = 1: operating) |
| D1RA | 25FE002CH | 8 | DMA level 1 read address addition value (=0: not added / =1: 4Byte addition) |
| D1RUP | 25FE0034H | 16 | DMA Level 1 Read Address Update Bit |
| D1R26-0 | 25FE0020H | 26-0 | DMA level 1 read address |
| D1WA2-0 | 25FE002CH | 2-0 | DMA level 1 write address addition value =000B: Do not add =001B: 2Byte addition =010B: 4Byte addition =011B: 8Byte addition =100B: 16Byte addition =101B: 32Byte addition =110B: 64Byte addition =111B: 128Byte addition |
| D1WT | 25FE007CH | 9 | DMA level 1 standby flag (=0: stop / =1: standby) |
| D1WUP | 25FE0034H | 8 | DMA level 1 write address update bit |
| D1W26-0 | 25FE0024H | 26-0 | DMA level 1 write address |
| D2C11-0 | 25FE0048H | 11-0 | DMA level 2 transfer bytes |
| D2EN | 25FE0050H | 8 | DMA level 2 permission bit (=0: Disable/=1: Enable) |
| D2FT2-0 | 25FE0054H | 2-0 | DMA level 2 activation factor selection bit =000B: V-blank-IN reception and permission bit set =001B: V-Blank-OUT reception and permission bit set =010B: H-Blank-IN reception and permission bit set =011B: Timer 0 reception and permission bit set =100B: Timer 1 reception and permission bit set =101B: Sound Req reception and permission bit set =110B: Sprite drawing end and permission bit set =111B: DMA activation bit set and permission bit set |
| D2GO | 25FE0050H | 0 | DMA level 2 activation bit (=0: stop/=1: start) |
| D2MOD | 25FE0054H | 24 | DMA level 2 mode bit (=0: Direct mode/=1: Indirect mode) |
| D2MV | 25FE007CH | 12 | DMA level 2 operating flag (=0: stopped / = 1: operating) |
| D2RA | 25FE004CH | 8 | DMA level 2 read address addition value (=0: not added / =1: 4Byte addition) |
| D2RUP | 25FE0054H | 16 | DMA Level 2 Read Address Update Bit |
| D2R26-0 | 25FE0040H | 26-0 | DMA level 2 read address |
| D2WA2-0 | 25FE004CH | 2-0 | DMA level 2 write address addition value =000B: Do not add =001B: 2Byte addition =010B: 4Byte addition =011B: 8Byte addition =100B: 16Byte addition =101B: 32Byte addition =110B: 64Byte addition =111B: 128Byte addition |
| D2WT | 25FE007CH | 13 | DMA level 2 standby flag (=0: stop / =1: standby) |
| D2WUP | 25FE0054H | 8 | DMA level 2 write address update bit |
| D2W26-0 | 25FE0044H | 26-0 | DMA level 2 write address |
| E | 25FE0080H | 18 | DSP program control port, program end interrupt flag |
| EP | 25FE0080H | 25 | DSP program control port, pause execution flag during program execution (=0: Not executed / = 1: Executed) |
| E.S. | 25FE0080H | 17 | DSP program control port, program step execution control bit (=0: Not executed / = 1: Executed) |
| EX | 25FE0080H | 16 | DSP program control port, program execution control bit (=0: Not executed / = 1: Executed) |
| IMS0 | 25FE00A0H | 0 | V-blank-IN interrupt mask bit |
| IMS1 | 25FE00A0H | 1 | V-blank-OUT interrupt mask bit |
| IMS2 | 25FE00A0H | 2 | H-blank-IN interrupt mask bit |
| IMS3 | 25FE00A0H | 3 | Timer 0 interrupt mask bit |
| IMS4 | 25FE00A0H | 4 | Timer 1 interrupt mask bit |
| IMS5 | 25FE00A0H | 5 | DSP end interrupt mask bit |
| IMS6 | 25FE00A0H | 6 | Sound request interrupt mask bit |
| IMS7 | 25FE00A0H | 7 | SMPC interrupt mask bit |
| IMS8 | 25FE00A0H | 8 | PAD interrupt mask bit |
| IMS9 | 25FE00A0H | 9 | Level 2 - DMA End Interrupt Mask Bit |
| IMS10 | 25FE00A0H | 10 | Level 1 - DMA End Interrupt Mask Bit |
| IMS11 | 25FE00A0H | 11 | Level 0-DMA end interrupt mask bit |
| IMS12 | 25FE00A0H | 12 | DMA illegal interrupt mask bit |
| IMS13 | 25FE00A0H | 13 | Sprite drawing end interrupt mask bit |
| IMS15 | 25FE00A0H | 15 | A-Bus interrupt mask bit |
| IST0 | 25FE00A4H | 0 | V-blank-IN interrupt status bit |
| IST1 | 25FE00A4H | 1 | V-blank-OUT interrupt status bit |
| IST2 | 25FE00A4H | 2 | H-blank-IN interrupt status bit |
| IST3 | 25FE00A4H | 3 | Timer 0 interrupt status bit |
| IST4 | 25FE00A4H | 4 | Timer 1 interrupt status bit |
| IST5 | 25FE00A4H | 5 | DSP end interrupt status bit |
| IST6 | 25FE00A4H | 6 | Sound request interrupt status bit |
| IST7 | 25FE00A4H | 7 | SMPC interrupt status bit |
| IST8 | 25FE00A4H | 8 | PAD interrupt status bit |
| IST9 | 25FE00A4H | 9 | Level 2 - DMA End Interrupt Status Bit |
| IST10 | 25FE00A4H | 10 | Level 1 - DMA End Interrupt Status Bit |
| IST11 | 25FE00A4H | 11 | Level 0 - DMA End Interrupt Status Bit |
| IST12 | 25FE00A4H | 12 | DMA illegal interrupt status bit |
| IST13 | 25FE00A4H | 13 | Sprite drawing end interrupt status bit |
| IST31-16 | 25FE00A4H | 31-16 | External interrupt 15-0 status bits |
| L.E. | 25FE0080H | 15 | DSP program control port, program counter load enable bit (=0: Not executed / = 1: Executed) |
| PD31-0 | 25FE0084H | 31-0 | DSP program RAM data port |
| PR | 25FE0080H | 26 | DSP program control port, pause release flag during program execution (=0: Not executed / = 1: Executed) |
| P7-0 | 25FE0080H | 7-0 | DSP program RAM address |
| RA7-0 | 25FE0088H | 7-0 | DSP data RAM address |
| RD31-0 | 25FE008CH | 31-0 | DSP data RAM data port |
| RSEL | 25FE00C4H | 0 | SD RAM selection bit (=0: 2Mbit×2/=1: 4Mbit×2) |
| S | 25FE0080H | 22 | DSP program control port, sign flag |
| TENB | 25FE0098H | 0 | Timer enable bit (=0: OFF/=1: ON) |
| T.O. | 25FE0080H | 23 | DSP program control port, D0 bus use DMA execution flag |
| T0C9-0 | 25FE0090H | 9-0 | Timer 0 compare data |
| T1MD | 25FE0098H | 8 | Timer 1 mode bit =0: Occurs on every line =1: Occurs only on the line specified by timer 0 |
| T1S8-0 | 25FE0094H | 8-0 | Timer 1 set data |
| V | 25FE0080H | 19 | DSP program control port, overflow flag |
| VER3-0 | 25FE00C8H | 3-0 | SCU chip version number |
| Z | 25FE0080H | 21 | DSP program control port, zero flag |