Figure 3.1 Block diagram of SMPC control mode
Figure 3.2 Setting example of SMPC control mode
register name | Setting value | Contents |
IOSEL1/2 | 0H | SMPC control mode |
EXL1/2 | 0H | PAD interrupt, VDP2 external latch disabled |
DDR1/2 | 00H | All bit input |
request to issue | Reception conditions | SMPC operation | |
conti | break | ||
× | × | on hold | Waiting for request |
× | ○ | break | Peripheral data collection is interrupted and INTBACK command is terminated. |
○ | × | Continue | Continued peripheral data collection |
○ | ○ | Ban | No warranty |
Figure 3.3 All peripheral data acquisition sequence
Figure 3.4 Peripheral data acquisition cancellation sequence due to break request