Chapter 2 Address Map

■2.1 Address map

The address map for VRAM, frame buffer, and system registers managed by VDP1 is as follows:

The addresses described in this chapter are relative addresses unless otherwise specified. Find the absolute address by adding 5C00000H.

Figure 2.1 Address map

               *3                       
               ┌───────────┐            
               │           │*1          
               │           │            
000000H~07FFFFH│   VRAM    │            
               │   4Mbit   │            
               │           │     *2     
               ├───────────┼───────────┐
               │           │           │
               │ Frame     │ Frame     │
080000H~0BFFFFH│ buffer 0  │ buffer 1  │
               │  2Mbit    │  2Mbit    │
               ├───────────┼───────────┘
0C0000H~0FFFFFH│ Reserved  │            
               ├───────────┤            
               │           │            
               │           │            
               │  System   │            
100000H~17FFFFH│ register  │            
               │           │            
               │           │            
               ├───────────┤            
               │           │            
               │           │            
               │  Access   │            
180000H~1fFFFFH│prohibited │            
               │           │            
               │           │            
               └───────────┘            

Note*1

VRAM stores the following table

・Command table

・Character pattern table

・Color lookup table

・Gouraud shading table

Note*2

There are two frame buffers from 080000 to 0BFFFFH.

Only the drawing surface is accessible. Display surface is not accessible.

●VRAM

• VRAM is 4Mbit DRAM.

• VRAM defines the command table, sprite character pattern table, color lookup table, and Gouraud shading table. Each piece of data can reside anywhere in VRAM and can be nested. Specify each address and refer to it.

• Command table fetching is always performed from the beginning of VRAM (000000H).

• Fetching VRAM is
  command table
  Gouraud shading table (only when using Gouraud shading)
  Color lookup table (only when using lookup table method)
  Character pattern table (only when drawing sprites)

  will be repeated in this order.

  If the command table fetch exceeds the VRAM end address (07FFFFH), the command table will be fetched back to the VRAM start address (000000H).

  Both byte and word accesses are possible from the CPU.

  Read/write access to VRAM from the system controller (system controller IC) and parameter read and pattern read access from VDP1 are performed with priority.

  VRAM access priority is always

  Syscon (system controller IC)＞ drawing

  This is the order.

  Access is prioritized, so depending on the timing, there may be a wait of about 10 or more clocks of the CPU operating clock. CPU operating clock is 28MHz.

  To prevent drawing from being interrupted, access from the CPU when drawing is not being performed. Determine whether drawing is in progress by polling the system register or using an interrupt signal. Also, use burst transfer to access VRAM and frame buffer in a short time.